Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
1996-04-19
2002-11-19
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S207000, C365S230060
Reexamination Certificate
active
06483742
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to sense and write path architectures for a semiconductor memory device and specifically to sense and write path architectures for nonvolatile semiconductor memory devices that include memory cells that store more than a single bit of data.
BACKGROUND OF THE INVENTION
Nonvolatile semiconductor memory devices are fundamental building blocks in prior art computer system designs. The primary means by which data is stored in nonvolatile memory is the memory cell. Typical prior memory technologies provide a storage capacity of one bit, or two states, per cell. Nonvolatile memory cells that have more than two possible states are known to the prior art.
One type of prior nonvolatile semiconductor memory is the flash electrically-erasable programmable read-only memory (“flash EEPROM”). Prior art flash EEPROMs typically allow for the simultaneous reading of several flash cells. Further, typical prior flash EEPROMs have a storage capacity that is much greater than the amount of data that can be output at any one time. Accordingly, each output of a flash EEPROM is typically associated with an array of flash cells that is arranged into rows and columns, where each flash cell in an array is uniquely addressable. When a user provides an address, row and column decoding logic in the flash EEPROM selects the corresponding flash cell. If more than one output is provided, the array is typically subdivided into equal-sized data blocks containing a subset of the number of columns in the array. For example, in a sixteen output flash device containing 512k flash cells arranged in 1024 rows and 512 columns, each of the sixteen data blocks contains 32 columns by 1024 rows of flash cells.
One type of prior flash cell is a field effect transistor (FET) that includes a select gate, a floating gate, a drain and a source. For read operations, the source of the flash cell is couple ground, and the drain of the flash cell is coupled to a bitline of the array. The flash cell is switched on and off by applying a select voltage to the select gate via a wordline that is coupled to the select gate. The extent to which the flash cell conducts current when the select voltage is applied is determined by the threshold voltage V
t
of the flash cell, which can be increased by trapping electrons on the floating gate. A typical method for storing information in a flash cell requires the trapping of excess electrons on the floating gate to increase the V
t
of the flash cell such that the current conducted by the memory cell is reduced when the select voltage is applied to the select gate. If the cell current is less than a reference current when the select voltage is applied, the flash cell is said to be “programmed.” If the cell current is greater than the reference current when the select voltage is applied, the flash cell is said to be “erased.” As the typical prior art flash cell is configured to be in one of two possible states, programmed or erased, the typical prior art flash cell is said to store one bit of data.
Typical prior art schemes for accessing data stored in a flash cell are therefore based on the premise that each cell stores a single bit of data. In such prior schemes, one output is provided for each selected cell, and addressing a particular memory cell is the same as addressing the data bit stored in the memory cell. When the memory cell stores two or more bits of data, however, the prior art sense path architectures for single bit cells are inadequate because each memory cell address specifies more than a single bit. A sense path architecture is therefore needed to access each bit of information stored in a memory cell that stores n bits of data. Similarly, a write path architecture is needed to write n bits of data per memory cell.
SUMMARY AND OBJECTS OF THE INVENTION
Therefore, one object of the present invention is to provide a sense path architecture for accessing each bit of a memory cell that stores n bits per cell.
Another object of the present invention is to provide a write path architecture for writing data to a memory cell that stores n bits per cell.
These and other objects are provided by a sense path circuit for accessing data stored in a selected memory cell that stores at least two binary bits of data. The sense path circuit includes a plurality of outputs equal in number to the n bits stored in the selected cell. The sense path circuit also includes a sensing circuit that is coupled to the selected memory cell and to each of the outputs for determining a state for each of the n bits stored in the selected memory cell and for outputting each of the n bits to a corresponding one of the plurality of outputs. A corresponding write path circuit is also disclosed.
A second embodiment provides for the objects of the invention by sense path circuit for accessing data stored in a selected memory cell that stores at least two binary bits of data. The sense path circuit includes a single output and a plurality of latches equal in number to the number of bits stored in the selected memory cell. The sense path circuit also includes a sensing circuit that is coupled to the selected memory cell and to each latch for determining a state for each of the n bits stored in the selected memory cell. A switching circuit selectively and sequentially couples the output of each latch to the output such that data stored in the selected memory cell is output over n consecutive clock cycles. A corresponding write path circuit is also disclosed.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description which follows below.
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PCT International Application Published under the PCT, International Pub. No. WO 90/12400, Pub. Date Oct. 18, 1990.
Bauer Mark E.
Sweha Sherif
Blakely , Sokoloff, Taylor & Zafman LLP
Hoang Huan
Intel Corporation
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