Bit map addressing schemes for flash memory

Details Bit map addressing schemes for flash memory Bit map addressing schemes for flash memory

1994-06-02

1996-03-05

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365207, G11C 800

Patent

active

054973546

ABSTRACT:
Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

REFERENCES:
patent: 4202044 (1980-05-01), Beilstein, Jr. et al.
patent: 4287570 (1981-09-01), Stark
patent: 4388702 (1983-06-01), Sheppard
patent: 4415992 (1983-11-01), Adlhoch
patent: 4586163 (1986-04-01), Koike
patent: 4653023 (1987-03-01), Suzuki et al.
patent: 4701884 (1987-10-01), Aoki et al.
patent: 4771404 (1988-09-01), Mano et al.
patent: 5012448 (1991-04-01), Matsuoka et al.
patent: 5043940 (1991-08-01), Harari
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5297148 (1994-03-01), Harari et al.
patent: 5351210 (1994-09-01), Saito
patent: 5375097 (1994-12-01), Reddy et al.

Affiliated with

Also associated with

Rating

Bit map addressing schemes for flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bit map addressing schemes for flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bit map addressing schemes for flash memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1417119