Bit manipulation circuitry in a microprocessor

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G06F 700, G06F 908

Patent

active

041942418

ABSTRACT:
A method and apparatus for bit manipulation in a digital processor being suitable for executing a plurality of instructions stored in a memory and carried from said memory in accordance with a plurality of machine cycles, each of said instructions including an operational code. A decoder generates a bit mask in response to an operational code. The bit mask generated is in binary digits which are the complement of 2.sup.i where i is the number in base 10 represented by the three least significant bits of the operational code. A register stores the particular bit-mask. An additional register stores a word in which a bit is to be manipulated. Logic circuitry performs one or more logic operations on the output of the registers whereby a desired bit in said word is manipulated. The output of the logic circuitry may be tested and depending on the result, a jump to a particular instruction stored in the memory may be made.

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