Static information storage and retrieval – Interconnection arrangements
Patent
1994-11-04
1996-08-27
Nelms, David C.
Static information storage and retrieval
Interconnection arrangements
365 51, 365 69, 365149, G11C 506, G11C 1124
Patent
active
055507697
ABSTRACT:
A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.
Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.
Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.
More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.
REFERENCES:
patent: 3942164 (1976-03-01), Dunn
patent: 4117545 (1978-09-01), Indachi
patent: 4476547 (1984-10-01), Miyasaka
patent: 4570241 (1986-02-01), Arzubi
patent: 4598387 (1986-07-01), Chuang et al.
patent: 4733374 (1988-03-01), Furuyama et al.
patent: 4748596 (1988-05-01), Ogura et al.
patent: 4757476 (1988-07-01), Fujishima et al.
patent: 4803663 (1989-02-01), Miyamoto et al.
patent: 4922459 (1990-05-01), Hidaka
patent: 4980860 (1990-12-01), Houston et al.
patent: 5214601 (1993-05-01), Hidaka et al.
patent: 5416734 (1995-05-01), Hidaka et al.
IBM J. Res. Develop.: "VLSI Wiring Capacitance", by Peter E. Cottrell et al., vol. 29, No. 3, May 1985, pp. 277-288.
Hidaka et al., "Twisted Bit-Line Architectures Technique for Multi-Megabit DRAM's", IEEE Journal of Solid-State Circuits, vol. 24, No. 1, (Feb.1989), pp. 21-27.
Yoshihara et al., "A Twisted Bit Line Technique for Multi-Mb DRAM's", 1989, IEEE International Solid-State Circuits Conference Digest of Technical Papers (Feb. 19, 1980), pp. 238-239.
Aoki et al., "A 60-ns 16-Mbit CMOS DRAM with a Transposed Data-Line Structure", IEEE Journal of Solid-State Circuits, vol. 23, No. 5 (Oct. 1988), pp. 1113-1119.
Chou et al., "A 60-ns 16Mbit DRAM with a Minimized Sensing Delay Caused by Bit-Line Stray Capacitance", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, (Oct. 1989), pp. 1176-1183.
W. Klein et al., "Symmetry Test", IBM Technical Disclosure Bulletin, vol. 27, No. 4A, Sep. 1984, pp. 2110-2111.
Fujishima Kazuyasu
Hidaka Hideto
Matsuda Yoshio
Dinh Son
Mitsubishi Denki & Kabushiki Kaisha
Nelms David C.
LandOfFree
Bit line structure for semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bit line structure for semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bit line structure for semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1060733