Bit line sharing and word line load reduction for low AC...

Details Bit line sharing and word line load reduction for low AC... Bit line sharing and word line load reduction for low AC...

2007-10-23

2007-10-23

Phan, Trong (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S189080, C365S203000

Reexamination Certificate

active

10215676

ABSTRACT:
In a SRAM structure, space and power saving is achieved by providing row and column select lines to select a specific bit cell, and reducing the number of bit lines in the structure used for writing to and reading from the bit cells. The number of bit lines is reduced by sharing bit lines of adjacent bit cells. Furthermore, in order to achieve power saving, the load on the row select lines is reduced by sharing the pass gates between adjacent bit cells that are used to control precharging, reading from and writing to the bit cells.

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