Bit line sensing in a memory array

Details Bit line sensing in a memory array Bit line sensing in a memory array

1995-11-15

1997-04-08

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

365208, G11C 1604

Patent

active

056194498

ABSTRACT:
A memory comprises first and second arrays of memory cells organised in rows and column. The cells in each row are connected to respective wordlines and the cells in each column are connected to a respective bit line. Wordlines of the first array are addressable independently of the wordlines of the second array. A sense amplifier is provided to sense the differential between a signal on the bit line of a selected cell in one array and a reference signal. A current souce is selectively connectable to supply the reference signal for comparison with the signal on the bit line of the addressed array. The present invention allows capacitive balancing to be achieved without the need for dummy cells.

REFERENCES:
patent: 4970691 (1990-11-01), Atsumi
patent: 5029138 (1991-07-01), Iwashita
patent: 5237530 (1993-08-01), Takashina
patent: 5237534 (1993-08-01), Tanaka
patent: 5331597 (1994-07-01), Tanaka
patent: 5440506 (1995-08-01), Longway
patent: 5487045 (1996-01-01), Trodden
Standard Search Report filed in the European Patent Office on Feb. 3, 1995.

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