Bit line selection decoder for an electronic memory

Details Bit line selection decoder for an electronic memory Bit line selection decoder for an electronic memory

1996-06-06

1998-09-29

Le, Vu A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 365 63, G11C 800

Patent

active

058154574

ABSTRACT:
A bit line selection decoder for an electronic memory having a plurality of bit lines in a plurality of groups includes a first set of a plurality of switches, each switch for selecting one of the plurality of bit lines in response to a control signal from a set of control lines applied to each group of bit lines. A second set of a plurality of switches is provided wherein each switch selects one group of the plurality of bit lines. The bit line selection decoder also includes a decoder which has a first input bus of control lines and a second input bus of control lines, wherein the control lines from the first and second input bus address any one of the plurality of groups of bit lines. The decoder has a plurality of outputs, wherein each output drives one switch in the second set of switches. The decoder may include a plurality of modules. Each module has a first input connected to receive one of the control lines from the second bus and a second input connected to receive the control lines of the first bus. The module includes a mechanism for activating a first output according to a combination of the first input and one of the control lines from the second input and a mechanism for activating a second output according to a combination of the first input and another of the control lines from the second input.

REFERENCES:
patent: 4916336 (1990-04-01), Houston
patent: 5297105 (1994-03-01), Matsui et al.
patent: 5371713 (1994-12-01), Ogiue et al.
patent: 5416748 (1995-05-01), Fujita
European Search Report from European Patent Application 95830267.1, filed Jun. 26, 1995.
1990 IEEE International Solid State Circuits Conference, Feb. 1990, S. Francisco, US pp. 132-281 Hirose et al., "A 20 NS 4MB CMOS SRAM with Hierarchical World Decoding Architecture".

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