Bit line selection circuit having hierarchical structure

Details Bit line selection circuit having hierarchical structure Bit line selection circuit having hierarchical structure

2002-09-25

2004-04-27

Phan, Trong (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C365S203000

Reexamination Certificate

active

06728125

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bit line selection circuit having a hierarchical structure and, more particularly, to a bit line selection circuit having a hierarchical structure capable of preventing delay of operation speed due to signal loading by selecting a bit line using a sub bit line selection driver in a hierarchically shared bit line sense amp.
2. Description of Related Art
Generally, a sense amp can be divided into a bit line sense amp and a data bus line sense amp. The bit line sense amp senses and amplifies that fine data signals stored in cell array are loaded on a bit line BL and a bit bar line /BL and then, transmits it to data bus line DB and data bus line bar /DB. The data bus line sense amp amplifies again data loaded on the data bus line DB and the data bus line bar /DB and then, transmits it to data output buffer.
In order to read out data from semiconductor memory cell, a row address is inputted and then, word line corresponding to the address is enabled. After a predetermined time (tRCD), a bit line sense amp is operated to latch cell data of enabled word line. Subsequently, when a column address is inputted, data of selected bit line sense amp is transmitted to data line sense amp through data line and then, amplified and transmitted to data output buffer.
FIG. 1
is a drawing showing operation and structure of conventional bit line selection circuit comprising: cell array units
1
a
and
1
b
, bit line equalizing units BLEQ
2
a
and
2
b
, bit line sense amp unit
3
, input output unit I/O
4
, bit line selection transistors N
4
, N
5
, N
6
and N
7
, and bit line selection signal generation units
5
a
and
5
b.
The bit line selection transistors N
4
, N
5
, N
6
and N
7
are controlled by bit line selection signals BS
0
and BS
1
, respectively, thereby operating a bit line selection transistor on the side of cell array unit selected by a column address signal
1
a
or
1
b
. The bit line selection signal generation units
5
a
and
5
b
generate the bit line selection signals BS
0
and BS
1
which has Vpp level when a bit line is selected, Vss level when a bit line is not selected and Vcc level when a bit line is precharged. That is, when the bit line is not selected, signal BSSUM
0
(or BSSUM
1
in
5
a
) inputted to the bit line selection signal generation unit
5
a
becomes ‘logic high’, thereby turning on N MOS transistor N
3
and lowering voltage of node Nd
4
to Vss.
On the other hand, when the bit line is not selected, the signal BSSUM
0
inputted to the bit line selection signal generation unit
5
a
becomes ‘logic low’, thereby turning on P MOS transistor P
2
and increasing voltage of node Nd
4
to Vcc level with N MOS transistor N
2
turned on. The input signal BSSUM
0
having ‘logic low’ is inputted to NAND gate NA
1
for inputting input signal N
300
(or N
301
in
5
b
) through inverter IV
3
-IN
5
of 3 steps. The output signal of the NAND gate NA
1
is level shifted through a level shifter unit
6
, thereby signal of node Nd
3
becomes ‘logic low’. Therefore, the N MOS transistor N
2
in turn on is turned off by the signal of the node Nd
3
‘low’ and P MOS transistor P
3
connected between Vpp and the node Nd
4
is turned on by the signal of the node Nd
3
‘low’, thereby increasing the node Nd
4
to Vpp level. Therefore, it is possible to select bit line selection transistors N
4
and N
5
in the bit line sense amp (BLSA) unit
3
and to read cell data or write data on cell. When BRSUM
0
(or BRSUM
1
in
5
b
) is high, the NMOS N
1
and the PMOS P
1
are switched on and allow the logical low or high signal of BSSUM
0
(or BRSUM
1
in
5
b
) to be received by the bit line selection signal generation unit
5
a
(or
5
b
). If on the other hand, BRSUM
0
(or BRSUM
1
in
5
b
) is high, both the P
1
and N
1
are switched off and do not allow the BSSUM
0
(or BRSUM
1
in
5
b
) signal to be received by the bit line selection signal generation unit
5
a
(or
5
b
).
However, the conventional bit line selection circuit has bit line selection transistors of many bit line sense amps in the selected bit line selection signal lines BS
0
and BS
1
, whereby loading is increased since memory density is increased. As a result, operation speed is delayed.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the above-mentioned problems and a primary objective of the present invention is to provide a bit line selection circuit having a hierarchical structure capable of preventing delay of operation speed due to loading of signal by selecting a bit line with a sub bit line selection driver in a hierarchically shared bit line sense amp structure.
In order to accomplish the above object, the present invention comprises: a bit line selection transistor unit for switching controlling a bit line between a cell array block and a bit lien sense amp; a bit line equalizing signal generation unit for receiving a sense amp enable signal and a first and a second block signals and generating a bit line equalizing signal; a global bit line selection unit driven by output signal of the bit line equalizing unit, for generating a first and a second global selection signals, a first and a second global selection bar signals and a bit line selection precharge signal; and a sub bit line selection driver unit for receiving the second global selection signal, the first global selection bar signal and the bit line selection precharge signal and generating a control signal controlling the bit line selection transistor unit.
Desirably, the sub bit line selection driver unit comprises: a pull up transistor for transmitting Vpp to a first signal line controlling the first bit line selection transistor unit by the first global selection bar signal; a pull down transistor for discharging a signal of the first signal line to ground voltage by the second global selection signal; and a precharge transistor for precharging the first signal line to source voltage by the bit line precharge signal. The pull up transistor comprises P MOS transistors. The pull down transistor comprises N MOS transistors. The precharge transistor comprises N MOS transistors.
Desirably, the bit line equalizing signal generation unit comprises flip flops comprising NOR gates for receiving the sense amp enable signal and a first and a second block signals. The global bit line selection unit receives and level shifts output signal of the flip flop and then, logic operates the level shifted signal to generate the first and second global selection bar signals and the bit line selection precharge signal.


REFERENCES:
patent: 5886943 (1999-03-01), Sekiguchi et al.
patent: 5917745 (1999-06-01), Fujii
patent: 5923605 (1999-07-01), Mueller et al.
patent: 5973983 (1999-10-01), Hidaka
patent: 6088286 (2000-07-01), Yamauchi et al.
patent: 6333869 (2001-12-01), Tanizaki et al.

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