Bit line reference circuits for binary and...

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185110, C365S185210, C365S185250, C365S189070, C365S189090, C365S189110, C365S207000

Reexamination Certificate

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07099188

ABSTRACT:
Auto-tracking bit line reference schemes have common reference and normal word lines and generate a “½ cell current” reference by providing reference bit lines with pull-up devices having a different effective size from the pull-up devices for bit line or by programming reference cells to different levels. To provide a true “current mirror” connection of the pull-up devices of bit line and one or more reference bit lines, an additional bias bit line causes currents through the pull-up devices for the selected bit line and the reference bit lines to mirror current through the pull-up device for the bias bit line. Embodiments of the invention can be used with binary and multiple-bit-per cell memory and with a variety of sense amplifiers, memory array architectures, and memory cell structures.

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