Bit-line pair selecting circuit in a memory cell array

Details Bit-line pair selecting circuit in a memory cell array Bit-line pair selecting circuit in a memory cell array

1994-04-11

1995-08-29

Popek, Joseph A.

Static information storage and retrieval

Addressing

Plural blocks or banks

365154, 36518902, G11C 800

Patent

active

054466997

ABSTRACT:
An SRAM cell comprising a flip-flop consisting of first and second inverters, and two word transistors connected to the flip-flop. In this cell, the gates of the word transistors are composed of a single word line, and the gate of a driver transistor in the first inverter is provided on one side of the word line, while the gate of a driver transistor in the second inverter is provided on the other side of the word line. The gate regions of the driver transistors in the first and second inverters are so formed as to partially overlap the bit-line side diffused layer regions of the word transistors. Also disclosed is a memory cell array comprising a plurality of cell rows each having a plurality of the above SRAM cells. In this array, the memory cells disposed in the even row are so arranged as to have a positional deviation of approximately half the cell length in the same direction respectively from the memory cells disposed in the odd row.

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