Bit line gain circuit for read only memory

Details Bit line gain circuit for read only memory Bit line gain circuit for read only memory

1984-11-20

1987-04-28

Moffitt, James W.

Static information storage and retrieval

Read only systems

Semiconductive

365189, G11C 1700

Patent

active

046619267

ABSTRACT:
A ROM memory circuit featuring a bit line gain circuit to the output thereof, effective for establishing isolation of bit and output lines, reduction of bit line voltage swing, VREF level tracking and bit line select circuitry performing a logical OR between two adjacent column select signals with no more than three transistors and effective for generation of a sinking current to maximize the slew rate of the output signal nodes.

REFERENCES:
patent: 4281397 (1981-07-01), Neal et al.
patent: 4348596 (1982-09-01), Atherton et al.
patent: 4388705 (1983-06-01), Sheppard
Wilson, "Cell Layout Boosts Speed of Low Power 64K ROM", Electronics, Mar. 30, 1978, pp. 96-99.

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