Bit line decoder architecture for NOR-type memory array

Details Bit line decoder architecture for NOR-type memory array Bit line decoder architecture for NOR-type memory array

2011-01-11

2011-01-11

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read only systems

C365S104000, C365S185170, C365S230030, C365S230060

Reexamination Certificate

active

07869247

ABSTRACT:
A bit line decoder for sensing states of memory cells of a memory array includes a first sub-decoder that (i) is adjacent to the memory array and (ii) includes D control devices arranged in a first of two levels of the bit line decoder. The D control devices selectively communicate with a first set of S of B bit lines of the memory array and are connected to each other in series forming (D−1) junctions. (S−2) of the S bit lines are directly connected to the (D−1) junctions, where log2D>2, S=(D+1), And S<B, and where D, S, and B are integers. A control module generates first and second control signals. The first control signals deselect two of the D control devices. An isolation circuit includes a plurality of isolation devices, each isolation device having (i) first ends that communicate with the first sub-decoder and (ii) second ends. The first ends selectively communicate with the second ends based on the second control signals.

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