Bit line decoder architecture for NOR-type memory array

Details Bit line decoder architecture for NOR-type memory array Bit line decoder architecture for NOR-type memory array

2011-01-11

2011-01-11

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read only systems

C365S104000, C365S185170, C365S230030, C365S230060

Reexamination Certificate

active

07869248

ABSTRACT:
A bit line decoder for sensing states of memory cells of a memory array includes R first sub-decoders that communicate with R memory sub-arrays of the memory array, respectively, where R is an integer greater than 1. Each of the R first sub-decoders includes D control devices that communicate with S bit lines of the memory array, where D and S are integers greater than 2, and S>D, (S-1) of the D control devices are connected in series with each other forming (S-2) junctions. The (S-2) junctions are directly connected to (S-2) of the S bit lines. R isolation circuits each have first ends that communicate with the R first sub-decoders, respectively, and second ends. The second ends of a first of the R isolation circuits communicate with corresponding second ends of (R-1) of the R isolation circuits. A second sub-decoder communicates with one of the R first sub-decoders via the second ends of the R isolation circuits. A sensing circuit communicates with the second sub-decoder and senses a state of one of the memory cells located within one of the R memory sub-arrays via the second ends.

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