Bit line decoder architecture for NOR-type memory array

Details Bit line decoder architecture for NOR-type memory array Bit line decoder architecture for NOR-type memory array

2011-01-11

2011-01-11

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read only systems

C365S104000, C365S185050, C365S185170, C365S230060

Reexamination Certificate

active

07869246

ABSTRACT:
A bit line decoder includes control devices that selectively communicate with bit lines and that are arranged in a multi-level configuration having a plurality of levels. Each of the levels includes a plurality of the control devices connected to each other in series forming one or more junctions. Each of the one or more junctions in one of the levels is directly connected to a respective one of the bit lines. A control module selects from the bit lines a first bit line and a second bit line associated with a memory cell when determining a state of the memory cell and generates first control signals that deselect one or more of the control devices at each of the levels. When the one or more control devices at each of the levels are deselected, a first group of the bit lines including the first bit line is charged to a first potential and a second group of the bit lines including the second bit line is charged to a second potential. An isolation circuit to isolate a first one of the levels from a second one of the levels includes a plurality of isolation devices having first ends that communicate with the control devices of the first one of the levels and second ends that communicate with the control devices of the second one of the levels.

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