Bit line decoder architecture for nor-type memory array

Details Bit line decoder architecture for nor-type memory array Bit line decoder architecture for nor-type memory array

2011-05-03

2011-05-03

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read only systems

C365S104000, C365S185050, C365S185170, C365S230060

Reexamination Certificate

active

07936581

ABSTRACT:
A bit line decoder for sensing states of memory cells of a memory array includes D control devices that selectively communicate with (D−1) bit lines of the memory array. (D−2) of the D control devices are arranged in a first level and two of the D control devices are arranged in a second level of the bit line decoder. The (D−2) control devices are connected to each other in series forming (D−3) junctions. (D−3) of the (D−1) bit lines are directly connected to the (D−3) junctions. Log2(D−2) is an integer greater than 2. A control module generates first control signals that deselect a predetermined number of the D control devices and that select two of the (D−1) bit lines that communicate with one of the memory cells. An isolation circuit to isolate the first level from the second level includes a plurality of isolation devices having first ends that communicate with the (D−2) control devices of the first level and second ends that communicate with the two control devices of the second level.

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International Search Report and the Written Opinion of the International Searching Authority, or the Declaration mailed Sep. 3, 2008 for International Application No. PCT/US2008/064881filed May 27, 2008; 12 pages.

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