Bit line control for low power in standby

Details Bit line control for low power in standby Bit line control for low power in standby

2007-11-20

2007-11-20

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Powering

Data preservation

C365S189090

Reexamination Certificate

active

11109224

ABSTRACT:
The present invention achieves technical advantages as embodiments of an SRAM cell (20, 30) having the bit line voltage (BLB/BLB) controlled during standby, such as allowing the bit line to float allowing the bit line voltage to be established by balance of leakage currents to the minimum leakage through the bit line. Advantageously, a controller (22, 32) also controls voltages of supplies Vdd, Vss and the n-well (Vnwell) voltage. The controller reduces a voltage differential between the supply voltage Vdd and voltage Vss in the standby mode. In one embodiment, the bit line may be tied to the reference voltage Vss, and a time delay may be introduced to reduce the possibility of using more charge in switching than that saved.

REFERENCES:
patent: 5726562 (1998-03-01), Mizuno
patent: 6166985 (2000-12-01), McDaniel et al.
patent: 6611451 (2003-08-01), Houston
patent: 6643208 (2003-11-01), Yamagata et al.
patent: 6657911 (2003-12-01), Yamaoka et al.
patent: 6885057 (2005-04-01), Osada et al.
Xiaowei Deng, et al., “A Low Leakage SRAM Scheme” U.S. Appl. No. 10/349,277, filed Jan. 22, 2003.

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