Bit line barrier metal layer for semiconductor device and...

Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity

Reexamination Certificate

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Details

C257S009000, C257S297000, C257S906000, C257S907000, C257SE21657, C257SE21658

Reexamination Certificate

active

11052403

ABSTRACT:
The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose an ion implantation region; vapor-depositing a first barrier metal layer of a Ti film on the entire upper surface thereof; and vapor-depositing, on the upper part of the Ti film, a second barrier metal layer of a ZrB2film having different upper and lower Boron concentrations, by RPECVD controlling the presence/absence of H2plasma, wherein the barrier metal layer includes the Ti film, lower ZrB2film and upper a ZrB2film sequentially stacked between tungsten bit lines and ion implantation region of a semiconductor substrate. Therefore, the present invention can decrease contact resistance between tungsten bit lines and an ion implantation region by utilizing a ZrB2film having near-amorphous film quality as a barrier metal of tungsten bit lines and thereby preventing diffusion of the dopant doped onto the ion implantation region of a substrate to the outside in a subsequent thermal treatment process, and at the same time, can reduce occurrence of parasitic capacitance between adjacent bit lines by decreasing a thickness of barrier metal layer, thus leading to improved characteristics of the semiconductor device.

REFERENCES:
patent: 5839363 (1998-11-01), Yanagisawa et al.
patent: 6632739 (2003-10-01), Watatani
patent: 6657265 (2003-12-01), Fujisawa et al.
patent: 2004/0070649 (2004-04-01), Hess et al.
patent: 1020010011307 (2001-02-01), None

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