Bit level pipeline divide circuit and method therefor

Details Bit level pipeline divide circuit and method therefor Bit level pipeline divide circuit and method therefor

1992-05-11

1994-08-23

Mai, Tan V.

Boots, shoes, and leggings

364766, G06F 752

Patent

active

053413229

ABSTRACT:
A divide circuit having bit level pipeline capability uses an array of bit level carry save adders with each carry save adder having a corresponding absolute value bit level circuit. In one or two's complement notation, the carry save adders subtract the binary values supplied thereto and generates an intermediate binary signal which is supplied to the absolute value circuit. The absolute value circuit determines the absolute value of the binary number supplied thereto. The circuit performs division in accordance with the following algorithm:
Q.sub.w 1
I=W-1 to 0
N=N-D
S=Signbit (N)
Q.sub.I =S (EXOR) Q.sub.I+1
N=.vertline.N.vertline.
D=D/2
END
A recursive divide circuit employing an array of carry save adders and absolute value bit level circuits achieves full pipeline bit level capability.

REFERENCES:
patent: 4872214 (1989-10-01), Zurawski
patent: 4891780 (1990-01-01), Miyoshi
T. E. Williams, M. A. Horowitz, "A zero-overhead self-timed 160ns 54-b CMOS divider", IEEE Journal Solid State Circuits; 26(11):1651-61, 1991.
A. Vandemeulebroecke, E. Vanzieleghem, T. Denayer, P. G. A. Jespers, "A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor"; IEEE Journal Solid State Circuits, 25(3); 748-56, 1990.
H. Edamatsu, T. Taniguchi, S. Kuninobu, "A 33 MFLOPS floating point processor using redundant binary representation"; In Proceedings IEEE ISSCC'88, pp. 152-153, 1988.

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