Bit gating for efficient use of RAMs in variable plane displays

Details Bit gating for efficient use of RAMs in variable plane displays Bit gating for efficient use of RAMs in variable plane displays

1987-11-03

1990-03-20

Harkcom, Gary V.

Boots, shoes, and leggings

340799, 340800, 364900, G09G 116

Patent

active

049106872

ABSTRACT:
Apparatus for serializing 2.sup.M parallel outputs of an all points addressable memory into successive data groups, with each data group corresponding to a respective value for a pixel in an image, wherein the bit-length of the pixel value is selectable. The apparatus includes a gate circuit having 2.sup.M parallel input junctions connected to the outputs of the memory and 2.sup.N output junctions. The gate circuit selectively converts each set of 2.sup.M parallel inputs at the input junctions in to 2.sup.M-n successive data groups, with each group having a bit-length of 2.sup.n bits. Each such group is transmitted to 2.sup.n of the 2.sup.N output junctions. A communication element conveys to the gate circuit a signal which controls the bit-length 2.sup.n of the data groups, wherein n is an integer 1.ltoreq.n.ltoreq.N.ltoreq.M.

REFERENCES:
patent: 4674064 (1987-06-01), Vaughn
patent: 4747081 (1988-05-01), Heilveil et al.
patent: 4777481 (1988-10-01), Craver
patent: 4791580 (1988-12-01), Sherrill et al.
patent: 4800380 (1989-01-01), Lowenthal et al.

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