Bit exactness support in dual-MAC architecture

Details Bit exactness support in dual-MAC architecture Bit exactness support in dual-MAC architecture

2006-10-10

2006-10-10

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S498000

Reexamination Certificate

active

07120661

ABSTRACT:
An arrangement (200) and method for bit exactness support in dual-MAC architecture by detecting when underflow or overflow conditions will occur, and for operating the dual-MAC arrangement in single-MAC mode for at least one cycle upon such detection.This produces the advantages of providing dual-MAC execution with saturation capabilities, with only a small degradation in performance, while employing detection logic that is very small and simple compared to the logic required for a conventional full saturation dual-MAC architecture.

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patent: 2005/0027774 (2005-02-01), Chauvel et al.
patent: 1058185 (2000-12-01), None
GB 0213177.9 Search Report.

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