Bit error rate detection system

Details Bit error rate detection system Bit error rate detection system

1996-05-17

1998-06-09

Chung, Phung

Excavating

371 51, G06F 1100

Patent

active

057646511

ABSTRACT:
A system for determining a data stream using a variable length window for sampling of erred bits in the data stream is disclosed. A threshold maximum-allowable error rate is selected; a first window length to comprise a data stream sample is selected; the data stream is monitored for errors during the given window length; the allowable error is compared to the total number of errors detected during the monitoring step; and, if the detected error is greater than the allowable error, the window length is reduced and monitoring is continued using the reduced window length, else monitoring continues over successive window length periods. A signal degrade or signal fail condition signal is generated if the window length reaches zero. The system can be utilized to implement an automatic protection switching system for a SONET network.

REFERENCES:
patent: 5307351 (1994-04-01), Websters
patent: 5561955 (1996-10-01), Jacobsmeyer

Affiliated with

Also associated with

Rating

Bit error rate detection system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bit error rate detection system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bit error rate detection system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2209943