Excavating
Patent
1997-02-10
1998-06-02
Canney, Vincent P.
Excavating
G06F 1100
Patent
active
057612161
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a bit error measurement system for testing a bit error rate, and more particularly, firstly, to a bit error measurement system which has a bit error test pattern generator and a bit error measurement apparatus for analyzing bit error rates of an output signal from a device under test by interchangeably switching between specific patterns and random patterns in real time. Secondly, this invention relates to a bit error test pattern generator which automatically switches clock edges of a multiplexing clock signal to be used for generating a high speed pattern by sequentially multiplexing parallel patterns generated by a pattern generator. Thirdly, this invention relates to a bit error measurement system which is able to specify and record positions of the pattern that involved in bit errors.
BACKGROUND ART
A first example of a conventional technology is show in the following.
Namely, a bit error test pattern generator/bit error measurement apparatus in the conventional technology is described below in which a test pattern is generated by interchanging specific patterns and random pattern in real time to analyze bit errors in the output signal from a device under test.
In a bit error measurement system, a test pattern of test speed up to several 10 GHz is applied to a device under test DUT, and performance of the DUT is analyzed by measuring a bit error rate while changing the test conditions.
In the conventional bit error measurement system, a test pattern to be given to the DUT is generated in either one of the two forms. One is a pseudo random binary sequence (PRBS) pattern generation and the other is a word pattern generation in which contents of a memory are repeatedly generated. This test pattern is supplied to the DUT, and the resultant outputs of the DUT is compared with expected pattern signals. The number of bit errors is counted and an error rate is calculated and displayed.
FIG. 5 shows an example of a test arrangement for a bit error measurement system. A test pattern signal 71.sub.pat and a clock signal 73 from a pattern generator 71 are provided to a DUT 74. The resultant output from the DUT 74 which is a signal 61 to be measured and a clock signal 60 are provided to a bit error measurement apparatus 75 whereby a bit error is measured.
FIG. 6 shows an internal structure of the pattern generator 71. For generating a test pattern to be supplied to the DUT 74, the pattern generator 71 includes a PRBS generator 71.sub.prbs which generates a PRBS (pseudo random binary sequence) pattern, and a WORD generator 71.sub.word which generates a word pattern based on the contents of a memory. Either one of the patterns is fixedly selected by a multiplexer (MUX) 71.sub.m and is provided with a desired amplitude and offset voltage by a buffer amplifier 71.sub.buf. Then the test pattern is applied to the DUT 74. The contents of the memory and other conditions for the pattern generation are set in advance through an external CPU (computer) to satisfy the desired test conditions.
In receiving the test pattern signal, the DUT shown in FIG. 5 outputs pattern data, which for example, may be the same data received as input data, to the bit error measurement apparatus 75. The bit error measurement apparatus 75 receives the output data from the DUT 74 and compares the data with expected pattern internally generated and counts the number of bits which do not match with one another, calculates a bit error rate, and displays the results.
FIG. 7 shows an internal structure of the bit error measurement apparatus 75. The received signal 61 that is to be measured is compared, by a comparator 65, with a reference pattern from a reference pattern generator 62. The number of bits which do not match with one another are counted by an error counter 70.
Since the position of the pattern sequence in the received signal 61 to be tested from the DUT 74 and the position of the bit sequence from the reference pattern generator 62 are undefined, the measurement apparatus includes a pattern sy
Nakajima Takayuki
Osawa Kazutaka
Shimawaki Kazuhiro
Shiroyama Kouichi
Sotome Tetsuo
Advantest Corp.
Canney Vincent P.
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