Bit error measurement circuit

Details Bit error measurement circuit Bit error measurement circuit

1996-09-26

1998-03-24

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057320896

ABSTRACT:
A bit error measurement circuit is designed to measure a number of bit errors by comparing receiving data with a reference Pseudo-Noise pattern. Herein, a certain PN pattern is used as the receiving data in order to perform testing in performance of communications and transmission by evaluating the receiving data. There are provided multiple kinds of PN patterns each having a specific PN-stage number. The bit error measurement circuit is capable of automatically detecting a PN-stage number with respect to the receiving data. One method to do so is to perform comparison between the receiving data and an arbitrary pattern at timings which are periodically set to correspond to all PN-stage numbers each having a probability to be related to the receiving data, wherein the arbitrary pattern is extracted from the receiving data. Thus, the PN-stage number is automatically detected in response to the timing at which the receiving data coincide with the arbitrary pattern. Another method is to extract consecutive-0s patterns and consecutive-1s patterns from the receiving data and to perform comparison between a count value, corresponding to a number of bits of a longest consecutive-0s pattern, and a count value corresponding to a number of bits of a longest consecutive-1s pattern. So, a PN-stage number and a logic are detected based on result of the comparison between the count values. Thus, a reference PN pattern is generated based on the PN-stage number and the logic.

REFERENCES:
patent: 5610940 (1997-03-01), Duvrant et al.
patent: 5633632 (1997-05-01), Ido et al.

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