Bit error detection circuit for PSK-modulated carrier wave

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375 34, H04B 1700, G06F 1100

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046285075

ABSTRACT:
A bit errror detection circuit for checking the quality of a transmission path by accurately predicting a true bit error rate (BER) despite changes in the operating point of a non-linear element or fluctuations in the level of an input signal. An inputted PSK-modulated carrier wave is separately phase demodulated by a recovered carrier wave and a phase modulated carrier wave. These two phase demodulated PSK-modulated carrier waves are inputted into separate discriminator circuits 412 and 413 having a common discrimination level where the difference between the outputs can be compared by the comparator circuit 409 to predict a true BER.

REFERENCES:
patent: 4034340 (1977-07-01), Sant' Agostino
patent: 4188615 (1980-02-01), Tan
patent: 4200838 (1980-04-01), Poitevin
patent: 4218771 (1980-08-01), Hogge, Jr.
patent: 4247938 (1981-01-01), Kurihara et al.
patent: 4367550 (1983-01-01), Douverne
patent: 4375099 (1983-02-01), Waters et al.
S. Takenaka et al., Bit Error Rate Monitor for Four Phase PSK Systems, Intl. Conf. on Communications, Seattle, WA, Jun. 8-12, 1980, pp. 25.1-25.6.
B. J. Leon et al., A Bit Error Rate Monitor for Digital PSK Links, IEEE Trans. on Comm., vol. COM-23, No. 5, May 1975, pp. 518-525.

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