Bit error detecting circuit for use in a digital signal transmis

Details Bit error detecting circuit for use in a digital signal transmis Bit error detecting circuit for use in a digital signal transmis

1978-08-15

1980-02-12

Atkinson, Charles E.

Communications: electrical

Digital comparator systems

325 41, G08C 2500

Patent

active

041886151

ABSTRACT:
A bit error detecting circuit for a digital signal transmission line of the type having a main decision circuit and a sub-decision circuit is disclosed. The purpose of the sub-decision circuit is to provide a prediction of a fault in the transmission, and this is accomplished without being adversely effected by a drift in the threshold level. A clock recovery circuit is responsive to the input digital signal to produce a clock signal which is supplied to both the main decision circuit and the sub-decision circuit and to a pattern generating circuit such as a binary counter. The main decision circuit decides the binary code of the input digital signal with respect to a first reference level. The binary code pattern from the pattern generating circuit is added to the input digital signal and the sum supplied to the sub-decision circuit which decides the binary code of the sum with respect to a second reference level. The outputs of the main decision circuit and sub-decision circuit are applied to an Exclusive OR circuit to provide a monitor output signal.

REFERENCES:
patent: 3701947 (1972-10-01), Van Der Houwen
patent: 4034340 (1977-07-01), Sant'Agostino
Gooding, Performance Monitor Techniques for Digital Receivers Based on Extrapolation of Error Rate, IEEE Trans. on Comm. Tech., vol. COM-16, No. 3, Jun. 1968, pp. 380-387.

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