Bit demultiplexor for demultiplexing a serial data stream

Details Bit demultiplexor for demultiplexing a serial data stream Bit demultiplexor for demultiplexing a serial data stream

1993-07-01

1996-06-11

Hsu, Alpus H.

Multiplex communications

Wide area network

Packet switching

370108, 370112, 375373, 327156, H03D 324, H04J 302

Patent

active

055263615

ABSTRACT:
A bit demultiplexing circuit is disclosed including an internal clock generator which, by a reference clock, generates a number of accurately mutually time delayed clock signals. Clock aligning devices are controlled by incoming serial data for providing, by the time delayed clock signals, a number of differently phase clock signals, the phase positions of which are set in dependence on the phase position of incoming data. First demultiplexing devices clock, by the differently phased clock signals, incoming serial data to a parallel data flow. Second demultiplexing devices align, by one of the differently phased clock signals, this data flow to outgoing parallel data. A bit multiplexor circuit is also disclosed and includes an internal clock, an aligner, a delay device, and a multiplexor.

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