Bit decoder for generating select and restore signals simultaneo

Details Bit decoder for generating select and restore signals simultaneo Bit decoder for generating select and restore signals simultaneo

1991-07-08

1994-05-31

Dixon, Joseph L.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365177, 365202, 365203, 307446, 307449, 307463, G11C 700, G11C 11413, G11C 800, H03K 1902

Patent

active

053175417

ABSTRACT:
A bit decoder for a memory array includes a decode NOR/OR circuit coupled to an output driver circuit. The decode NOR/OR circuit includes a plurality of input signals connected to respective input FET's all of which are connected in parallel between a common source and a common drain node. One input is also connected to an active pullup FET which is connected in series with the input FET's at the common drain node and which is always maintained slightly on. A bipolar transistor pulls down the common drain node and a bleeder FET pulls down the common source node. The output driver is a BICMOS circuit that provides both the bit selection and bit refresh signals which are of opposite phase.

REFERENCES:
patent: 3541353 (1970-11-01), Seelbach et al.
patent: 3614467 (1971-10-01), Tu
patent: 3942162 (1976-03-01), Buchanan
patent: 4090255 (1978-05-01), Berger et al.
patent: 4099162 (1978-07-01), von Basse
patent: 4104735 (1978-08-01), Hofmann et al.
patent: 4112314 (1978-09-01), Gani et al.
patent: 4185320 (1980-01-01), Takemae et al.
patent: 4198700 (1980-04-01), Aoyama et al.
patent: 4330851 (1982-05-01), White, Jr.
patent: 4429374 (1984-01-01), Tanimura
patent: 4455627 (1984-06-01), Oritani
patent: 4514829 (1985-04-01), Chao
patent: 4528646 (1985-07-01), Ochii et al.
patent: 4558234 (1985-12-01), Suzuki et al.
patent: 4563754 (1986-01-01), Aoyama et al.
patent: 4578779 (1986-03-01), Chan et al.
patent: 4596002 (1986-06-01), Chan et al.
patent: 4598390 (1986-07-01), Chan
patent: 4604533 (1986-08-01), Miyamoto et al.
patent: 4612631 (1986-09-01), Ochii
patent: 4616146 (1986-10-01), Lee et al.
patent: 4636983 (1987-01-01), Young et al.
patent: 4636990 (1987-01-01), Buscaglia et al.
patent: 4638186 (1987-01-01), McLaughlin
patent: 4639898 (1987-01-01), Sauer
patent: 4644500 (1987-02-01), Yonezu et al.
patent: 4649295 (1987-03-01), McLaughlin et al.
patent: 4658381 (1987-04-01), Reed et al.
patent: 4661723 (1987-04-01), Masuda et al.
patent: 4668879 (1987-05-01), Dansky et al.
patent: 4678940 (1987-07-01), Vasseghi et al.
patent: 4694202 (1987-09-01), Iwamura et al.
patent: 4694433 (1987-09-01), Wiedmann
patent: 4701642 (1987-10-01), Pricer
patent: 4713796 (1987-12-01), Ogiue et al.
patent: 4728827 (1988-03-01), Woo
patent: 4730279 (1988-03-01), Ohtani
patent: 4733110 (1988-03-01), Hara et al.
patent: 4739497 (1988-04-01), Itoh et al.
patent: 4740921 (1988-04-01), Lewandowski et al.
patent: 4746817 (1988-05-01), Banker et al.
patent: 4752913 (1988-06-01), Chan et al.
patent: 4779014 (1988-10-01), Masuoka et al.
patent: 4817057 (1989-03-01), Kondo et al.
patent: 4831285 (1989-05-01), Gaiser
patent: 4858194 (1989-08-01), Terada et al.
patent: 4862421 (1989-08-01), Tran
patent: 4866674 (1989-09-01), Tran
IBM Technical Disclosure Bulletin, vol. 17, No. 11, pp. 3338-3339, R. Linton et al., "Low-Power FET Storage Cell."
IBM Technical Disclosure Bulletin, vol. 28, No. 11, p. 5112, R. Kroesen et al., "Receiver Circuit with Differential Current Switch Logic Output."
IEEE Journal of Solid-State Circuits, vol. sc-21., No. 5, pp. 681-685, K. Ogiue et al., "13-ns, 500-mW, 64-kbit ECL RAM Using HI-BICMOS Technology".
IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1041-1047, H. Tran et al., "An 8-ns 256K ECL SRAM with CMOS Memory Array and Battery Backup Capability."
IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1048-1053, R. Kertis et al., "A 12-ns ECL I/O 236K X 1-bit SRAM Using A 1-um BICMOS Technology."
IEEE International Solid-State Circuits Conference Digest of Technical Papers, M. Odaka et al., "A 512 kb/5 ns BiCMOS RAM With 1 kG/150 ps Logic Gate Array."
1989 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, W. Heimsch et al., "Merged CMOS/Bipolar Current Switch Logic."
1989 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, H. Tran et al., "An 8 ns BiCMOS 1 Mb ECL SRAM With a Configurable Memory Array Size."
1989 IEEE International Solid-State Cirucits Conference, Digest of Technical Papers, M. Suzuki et al., "A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM."

Affiliated with

Also associated with

Rating

Bit decoder for generating select and restore signals simultaneo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bit decoder for generating select and restore signals simultaneo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bit decoder for generating select and restore signals simultaneo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1633131