Electrical pulse counters – pulse dividers – or shift registers: c – Applications – Including memory
Reexamination Certificate
1999-12-15
2001-11-27
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Applications
Including memory
C377S111000, C377S117000
Reexamination Certificate
active
06324238
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a bit counter stage, particularly for memories. More particularly, the invention relates to a bit counter stage with the associated external address loading path for memories and the like.
It is known that counters are used in a wide variety of situations, one of the most important being the counting of memory addresses.
It is known that a counter is provided by means of a plurality of cascade-connected counter stages, each stage being meant to count one of the bits of, for example, a memory address.
The sum of two binary numbers generates a carry value which must propagate along the counter, through the various stages of the counter, in order to obtain a correct sum.
The carry calculation time is the fact that limits the operating frequency of a counter.
Execution of the carry operation, i.e., its writing time, is the least time-consuming operation; carry generation instead limits and penalizes the operating frequency of said counter.
Owing to the need to increase ever more the operating frequency of the counter and therefore to reduce the period of its operation, in conventional counters in which said period is divided evenly between the carry generation step and the carry calculation step the carry generation step, which is the most penalizing one, may not have enough time available for its execution, whereas the carry execution step has an assuredly excessive amount of time available.
Moreover, any counter has a loading system which allows to load the initial configuration from outside. It is normally believed that loading management performed by means of an ALE control signal is generally free from reliability problems, but in actual fact there are severe difficulties due to the capability to distribute the current count produced by the counter. In conventional counters, the ALE (address latch enable) address in fact can generate a false count in the counter if the ALE signal is “dirty”, i.e., accidental, or if it is not an actual ALE signal.
In this case, the configuration assumed in the counter is destroyed in favor of a configuration which is set externally and the count resumes from the new loading instead of from the current calculation. This should not occur.
This situation becomes severe if the counter is directly interfaced with input structures, and in this case the problems involved in preventing possible false updates of the counter become very important.
SUMMARY OF THE INVENTION
The aim of the present invention is to provide an address counter stage, particularly for memories, in which the cycle of the counter is managed with a time-division mode which minimizes the carry execution interval and maximizes the carry creation and propagation interval.
Within the scope of this aim, an object of the present invention is to provide a bit counter stage, particularly for memory addresses, in which the asymmetry of the working cycle of the counter stage allows to raise the operating frequency of said stage.
Another object of the present invention is to provide a bit counter stage, particularly for memory addresses, in which the data item in input to the stage is presented to the actual counter stage with a delay technique which is suitable to filter false pulses and is such as to ensure the validity of the operation that must be performed by the counter.
Another object of the present invention is to provide a bit counter stage in which the updating steps of each stage of the counter are managed with a technique which guarantees the absence of “chasing” in the various steps and of unwanted acceleration of said steps.
Another object of the present invention is to provide a bit counter stage, particularly for memory addresses, in which there is no influence of external stimuli (data) during the counting step of the counter.
Another object of the present invention is to provide a bit counter stage, particularly for memory addresses, which can be used with very fast memories and with low supply voltages.
Another object of the present invention is to provide a bit counter stage, particularly for memory addresses, which is highly reliable, relatively easy to manufacture and at competitive costs.
This aim, these objects and others which will become apparent hereinafter are achieved by a bit counter stage, particularly for memory addresses, comprising:
master storage means;
slave storage means which are connected to said master storage means;
means for enabling the transit of an external address in said master storage means;
means for enabling the connection between said slave storage means and said master storage means;
means for enabling the connection between said master storage means and said slave storage means;
means for calculating the product of said external address and of an input carry signal which arrives from a preceding counter stage; and
means for calculating an output carry signal on the basis of said external address and of said input carry signal.
REFERENCES:
patent: 6078636 (2000-06-01), Shirai et al.
Jenkens & Gilchrist P.C.
STMicroelectronics S.r.l.
Wambach Margaret R.
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