Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-12-17
2004-06-15
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S236000
Reexamination Certificate
active
06751158
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a bit counter, and a program circuit in a semiconductor device and a method of programming the semiconductor device using the same. More particularly, the invention relates to a bit counter capable of reducing a program operation time upon the program operation, and a program circuit in a nonvolatile memory device including EEROM (electrically erasable and programmable read only memory) series and a method of programming the semiconductor device using the same.
2. Description of the Prior Art
In a memory cell of EEPROM (electrically erasable and programmable read-only memory) being a kind of a nonvolatile semiconductor device, a program operation is performed in which electrons are accumulated at a floating gate electrode. A read operation for data is performed by detecting variation in the threshold voltage depending on existence of the electrons. The EEPROM includes a flash EEPROM (hereinafter, called ‘flash memory device’) in which an erase operation of data is performed for the entire memory cell array or the erase operation of data is performed for the memory cell array in a block unit by dividing the memory cell array into given blocks.
Generally, the memory cells of the flash memory device can be classified in to a stack gate type and a split gate type, depending on its structure. The program operation of the stack gate type memory cell is mainly divided into a program step and a program-verify step. Biases at each of the steps is indicated in Table 1 below.
TABLE 1
Step
Program Step
Program-Verify Step
Gate Voltage
9 V
6 V
Drain Voltage
4 V
1 V
Source Voltage
0 V
0 V
Generally, the program operation is one by which the threshold voltage of the memory cell in the flash memory device is increased to a target threshold voltage. In the program step, the threshold voltage of a corresponding memory cell is increased by injecting electrons into the floating gate electrode through injection of hot carriers. In the program-verify step, the program operation is stopped at an adequate level by sensing variation in the amount of the target threshold voltage during the program step.
Based on Table 1, the program operation of the memory cell in the flash memory device will be described by reference to FIG.
6
and FIG.
7
. At this time,
FIG. 6
is a cross sectional view of the memory cell for explaining the program step of the flash memory device and
FIG. 7
is a cross sectional view of the memory cell for explaining the program-verify step of the flash memory device. Meanwhile, the gate electrode of a stack structure shown in FIG.
6
and
FIG. 7
includes a gate oxide film
608
, a floating gate electrode
610
, a dielectric film
612
and a control gate electrode
614
. The semiconductor substrate
602
includes a P-well, a source
604
and a drain
606
Referring now to
FIG. 6
, in the program step of the program operation, a gate voltage of 9V is applied to the control gate electrode
614
, a drain voltage of 4V is applied to the drain
606
, and 0V (ground; GD) is applied to the source
604
and the P-well, as indicated in Table 1. Thereby, as shown by an arrow direction, the hot carriers are moved from the source
604
to the drain
606
and the floating gate electrode
610
. The electrons are thus injected into the floating gate electrode
610
, so that the threshold voltage of the memory cell is increased.
By reference to
FIG. 7
, in the state that the electrons are injected into the floating gate electrode
610
through the program step in
FIG. 6
, if it is determined that the threshold voltage reaches a target value by sensing real time the threshold voltage of the memory cell, a program-verify step is performed by applying the gate voltage of 6V to the control gate electrode
114
of the main cell (MC), the drain voltage of 1V to the drain, the gate voltage of 3V to the control gate electrode
614
of a reference cell (RC) and the drain voltage of 1V to the drain. At this time, the program-verify step may be changed depending on the bias condition of the reference cell (RC) connected to the main cell (MC) and the sense amplifier.
The entire program operation is repeatedly performed for the entire memory cells. An example of this will be below described by reference to the flowchart shown in FIG.
8
.
For example, the program operation may be performed for the entire memory cells in a word unit (i.e., 16 bits). In this case, the program step and the program-verify step are first performed for all corresponding memory cells including in the word unit (S
810
and S
820
). Next, it is determined whether there exist failed memory cells of the corresponding memory cells included in the word unit, in the program step and the program-verify step (S
830
). As a result of determination, if it is determined that failed cells exist in the step (S
830
), the program step and the program-verify step are performed for the failed cells (S
840
and S
850
). These processes are repeatedly performed until failed memory cells do not exist.
Generally, in case that the program operation is performed in the word unit, the program current flowing from the drain to the source is very high. In order to increase the program efficiency and to reduce the operating current of the drain pump, the program operation is internally performed in a byte unit. In other words, upon the program operation of the byte unit, the program step is first performed for the I/O (input/output)<7:0>(i.e., 8 bits) and the program step is then performed for a next I/O<15:8>(i.e., 8 bits). Next, the program-verify step is performed for the I/O<15:0>(i.e., 16 bits) at a time. If there occurred any fail, the above processes are repeatedly performed. If any fail does not exist, the program operation is finished.
However, as shown in distribution of the entire memory cells shown in
FIG. 9
, upon the program operation, there exist marginal cells (that is, cells corresponding to the cut line in the pass) at an ‘A’ portion (point where the threshold voltage of the cell is 4.5V). In this state, if the program-verify step is performed, there may occur a case that the marginal cells are again determined to be a fail depending on the margin of the bias, even though they were determined to be passed.
As described above, if the program operation is repeatedly performed since the failed cells exist, a program pulse is always applied twice every 8 bit even though there exist passed bits among the 16 cells. In other words, assuming that the program time is 5 &mgr;s, the program time is increased by an integer times every time when the failed cells occur ‘5×2=10 &mgr;s’. Therefore, it causes to not only give a burden to the pumping circuit for supplying the bias upon the program operation but also increase the total time of the program operation. Further, there is a problem that the retention capability of data is degraded due to over-program since the bias is repeatedly applied to the already-programmed cells,
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to provide a bit counter capable of reducing a program operation time upon the program operation.
Another object of the present invention is to provide a program circuit of a semiconductor device using the bit counter.
Still another object of the present invention is to provide a method of programming the semiconductor device using the bit counter.
In order to accomplish the above object, the bit counter according to the present invention, is characterized in that it comprises a plurality of clock generators corresponding to program data inputted, wherein the clock generators are synchronized to the program data to be programmed, among the program data, to generate different clock signals, and a counter synchronized to the clock signals outputted from the clock generators and sequentially shifting the input data, upon synchronization, to count the number of bits of the program data
Hynix / Semiconductor Inc.
Le Vu A.
Morgan & Lewis & Bockius, LLP
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