Bit cells having offset contacts in a memory array

Details Bit cells having offset contacts in a memory array Bit cells having offset contacts in a memory array

2005-03-08

2005-03-08

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S204000, C257S206000, C257S208000, C257S209000, C257S211000

Reexamination Certificate

active

06864518

ABSTRACT:
According to one exemplary embodiment, a semiconductor data array comprises an active segment situated on a substrate. The semiconductor data array can be, for example, a ROM array. The semiconductor data array further comprises a first word line situated over the active segment and a second word line situated substantially parallel to the first word line, where the second word line is not situated over the active segment. The semiconductor data array further comprises a column situated over the active segment, the first word line, and the second word line. The semiconductor data array further comprises a contact situated on the active segment, where the contact couples the active segment to the column, where the contact is separated from the first word line by a first distance and from the second word line by a second distance, and where the first distance is less than the second distance.

REFERENCES:
patent: 6137713 (2000-10-01), Kuroda et al.

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