Bit buffer system

Multiplex communications – Wide area network – Packet switching

Patent

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Details

375119, 370100, H04J 306

Patent

active

043597700

ABSTRACT:
A bit buffer system wherein transmission data signals are sequentially stored in a shift register having a predetermined number of stages, the transmission data signal is taken out of a substantially central one of the predetermined number of stages at the time of initialization to be sent to a receiving unit, and the phase difference between the timing pulse controlling the period of the transmission data signal and the timing pulse controlling the operation of the receiving unit to select a specified stage of the shift register so as to take out the transmission data signal therefrom according to a detected phase difference. A specified code contained in the transmission coded data signal is detected to effect the initialization.

REFERENCES:
patent: 3908084 (1975-09-01), Wiley
patent: 4045618 (1977-08-01), Lagarde et al.

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