Bit and symbol timing recovery for sequential decoders

Details Bit and symbol timing recovery for sequential decoders Bit and symbol timing recovery for sequential decoders

1989-05-24

1992-01-07

Beausoliel, Robert W.

Excavating

371 46, G06F 1110

Patent

active

050797719

ABSTRACT:
In a sequential decoding apparatus, a sequential decoder performs sequential decoding on convolutional code symbols stored in a data buffer according to the maximum likelihood algorithm. When the buffer is overflowed due to random noise, the sequential decoder skips a portion of the stored symbols, clears its internal state and initiates a stepwise decoding on symbols of newly arrival. A sync detector detects that a count of symbols that have been decoded after the occurrence of the overflow is lower or higher than a predetermined value. If the overflow condition still exists following the stepwise decoding, a portion of the stored symbols is further skipped and the stepwise decoding is repeated. If the overflow condition ceases to exist and if the decoded symbol count is still lower than the predetermined value, the symbol skipping and stepwise decoding are repeated until it becomes higher than the predetermined value to cause the sequential decoder to resume normal operation.

REFERENCES:
patent: 4578800 (1986-03-01), Yasuda
patent: 4710746 (1987-12-01), Shimoda
patent: 4878221 (1989-10-01), Shimada

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