Bit aligned data block transfer method and apparatus

Details Bit aligned data block transfer method and apparatus Bit aligned data block transfer method and apparatus

1993-10-12

1994-09-13

Shaw, Dale M.

395425, G06F 1562

Patent

active

053476310

ABSTRACT:
The number of required clock periods in a bit aligned block transfer operation may be reduced by analyzing the logical relationship between source, destination and pattern operands prior to fetching these operands from memory. If the result of the raster operation can be determined without actually using the value of any of the operands, the result is provided without reading memory values. When the raster operation will have no effect on the existing destination operand, the write operation is also canceled.

REFERENCES:
patent: 4672680 (1987-06-01), Middleton
patent: 4692944 (1987-09-01), Masuzaki et al.
patent: 4860248 (1989-08-01), Lumelsky
patent: 4897636 (1990-01-01), Nishi et al.

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