Bisynchronous host/terminal communication system with non-clock-

Details Bisynchronous host/terminal communication system with non-clock- Bisynchronous host/terminal communication system with non-clock-

1981-06-16

1984-04-24

Thomas, James D.

Boots, shoes, and leggings

370 85, 3408255, G06F 304, G06F 300

Patent

active

044451938

ABSTRACT:
A communication adapter circuit (10) is connected to a processor through processor I/O interface buses (12, 14). Data and control signals are provided through the buses (12, 14) to a timer circuit (18), a programmable peripheral interface circuit (20), an asynchronous and bisynchronous control circuit (22) and an SDLC/HDLC control circuit (24). Each of the control circuits (22, 24) includes parallel-to-serial and serial-to-parallel conversion circuitry. A clock select circuit (32) operates in conjunction with the timer circuit (18) and the programmable peripheral interface circuit (20) to establish a data transmission rate for the data flow through the adapter circuit (10). From the control circuits (22, 24) the data is transmitted through a modem interface bus (44) to a dual modem switch (56). From the switch (56) the data is transmitted to either an EIA RS 232 interface circuit (60) to a conventional modem or through a bus (64) to an internal modem. A phase locked loop (PLL) circuit in the control circuit (24) generates a data clock signal on a line (33) for operation of the adapter circuit (10) in the bisynchronous protocol with a non-clock-generating modem.

REFERENCES:
patent: 3430204 (1969-02-01), Milford
patent: 3889064 (1975-06-01), Fletcher
patent: 4065862 (1978-01-01), Meyer
patent: 4227178 (1980-10-01), Gergaud et al.
patent: 4247908 (1981-01-01), Lockhart, Jr. et al.
patent: 4249266 (1981-02-01), Nakamori
patent: 4270150 (1981-05-01), Diermann et al.
patent: 4281380 (1981-07-01), De Mesa
patent: 4358825 (1982-11-01), Kyu et al.
D. M. Nagel, Asynchronous Receiver with Character Insert, IBM Technical Disclosure Bulletin, vol. 19, No. 8 (Jan. 1977).

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