Bistable logic device using trench transistors

Details Bistable logic device using trench transistors Bistable logic device using trench transistors

1991-03-26

1992-06-16

Wojciechowicz, Edward J.

357 236, 357 41, 357 42, 357 45, 357 55, H01L 2910

Patent

active

051228467

ABSTRACT:
The described embodiments of the present invention show a structure and process for fabricating this structure in which a bi-stable logic device, such as a static random access memory cell, is formed. The advantages of the described embodiments are most particularly found when in an array. In two parrallel lines formed in buried diffusions beneath the surface of the integrated circuit, V.sub.dd or the power supply voltage and ground are alternately provided. Two vertical transistors control conduction between ground and a surface diffusion are formed being connected to the buried ground diffusion. Two additional transistors are formed as load devices connected between the surface diffusion and the V.sub.dd buried diffusion. The surface diffusion is connected to complementary bit lines via access transistors formed connecting the surface diffusion to contact points for the complementary bit lines. By using buried ground and supply lines, large space savings may be obtained with the present memory cell. In addition, because of the vertical structure of all devices inthe memory cell, increased soft error immunity is obtained. Further space savings are achieved by the use of local interconnect processing for forming interconnections between surface devices in the cells. In another embodiment, a buried diffusion is used as an interconnection node for a bi-stable device using vertical devices.

REFERENCES:
patent: 4214917 (1980-07-01), Clark et al.
patent: 4653025 (1987-03-01), Minato et al.
patent: 4794561 (1988-12-01), Hsu
patent: 4835589 (1989-05-01), Pfiester
patent: 4881105 (1989-11-01), Davari et al.

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