Bistable logic circuit with in-service test capability

Details Bistable logic circuit with in-service test capability Bistable logic circuit with in-service test capability

1975-01-02

1976-07-20

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307215, 307247R, 307293, H03K 1700

Patent

active

039708730

ABSTRACT:
A bistable logic circuit generating a stable, preferred output logic state for activating a circuit load having a known response time and capable of being tested while installed and in service without activating the output load includes preferential output state logic memory means, asymmetric delay means and first logic means to generate an output which is the logic product of the memory output and the negation of the circuit Reset input. Second logic means generates the memory means control signal as the logic sum of the circuit Set input and the circuit output asymmetrically delayed by a time period less than the load response time. A test pulse output having a time duration less than the load response time is generated for a set input having a time duration less than one internally determined time period whereby the circuit load is not activated. A load activating output is generated at any time, including the test time period, for a Set input having a time duration greater then another internally determined time period and maintained until a Reset input is solely present.

REFERENCES:
patent: 3833853 (1974-09-01), Milford
patent: 3870953 (1975-03-01), Boatman et al.

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