Bistable flip-flop

Details Bistable flip-flop Bistable flip-flop

1998-11-09

2000-11-28

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327199, 327200, 327211, 327212, H03K 302

Patent

active

061540773

ABSTRACT:
In a known bitable flip-flop, a first inverter stage (1) is driven by an input signal (D), a second inverter stage (2) by a clock signal (CLK), and a third inverter stage (3) by an output signal (INV2) of the second inverter stage (2). In order to buffer the output signal levels of the inverter stages, the first and third inverter stages (1, 3) can be switched into a disabling state by the clock signal (CLK) and the second inverter stage (2) by an output signal (INV1) of the first inverter stage (1). The new bistable flip-flop is to be set independently of the input signal. For setting the flip-flop, preferably of CMOS design, field-effect transistors (M10, M11) are provided in the third and second inverter stages (3, 2) which inhibit disabling of the third inverter stage (3) by a set signal (SET) and a signal (SETN) that is complementary to it and which allow disabling of the second inverter stage (2) independently of the output signal (INV1) of the first inverter stage (1). The invention is useable in counter modules/frequency dividers.

REFERENCES:
patent: 4521695 (1985-06-01), Mazin
Patents Abstracts of Japan, Sect. E, vol. 18, No. 661 (E-1644) (Dec. 14, 1994).
Patents Abstracts of Japan, Sect. E, vol. 12, No. 342 (E-658) (Sep. 14, 1988).

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