Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2011-04-04
2011-10-11
Patel, Paresh (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
08035407
ABSTRACT:
An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal. A phase detector determines a phase difference between the selected internal data strobe input signal and the selected phase shifted data strobe output signal and outputs a phase difference value.
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patent: 7657803 (2010-02-01), Chae
Agrawal Vinay
Jarboe, Jr. James Michael
Nayak Neeraj P.
Panigrahi Sukanta Kishore
Bassuk Lawrence J.
Brady W. James
Patel Paresh
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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