Bist DDR memory interface circuit and method for...

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor

Reexamination Certificate

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Reexamination Certificate

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07834615

ABSTRACT:
An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal. A phase detector determines a phase difference between the selected internal data strobe input signal and the selected phase shifted data strobe output signal and outputs a phase difference value.

REFERENCES:
patent: 6452849 (2002-09-01), Iwamoto
patent: 7126366 (2006-10-01), Ohashi et al.
patent: 7457174 (2008-11-01), Braun et al.

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