BIST circuit for measuring path delay in an IC

Details BIST circuit for measuring path delay in an IC BIST circuit for measuring path delay in an IC

2006-02-07

2006-02-07

Miska, Vit W. (Department: 2841)

Horology: time measuring systems or devices

Time interval

Electrical or electromechanical

C714S727000, C714S733000, C324S763010, C324S765010

Reexamination Certificate

active

06996032

ABSTRACT:
A BIST circuit for an IC measures the time delay a rising or falling edge experiences as it passes through a signal path within the IC. A strobe circuit within the BIST circuit generates edges in two signals A and B in delayed response to edges of a STROBE signal. A path probe generates a signal C edge at the signal path input in response to each signal A edge. The STROBE-to-B edge delay within the strobe generator is iteratively adjusted to determine a first delay for which the path probe detects the B and C signal edges at nearly the same time and thereafter iteratively adjusted to determine a second delay for which the path probe detects the B and D signal edges at nearly the same time. The first delay is measured by causing the strobe signal generator to produce a periodic signal having a period proportional to the first delay and counting the number of cycles of a reference clock occurring during K cycles of the periodic signal. The second delay is measured in a similar manner. The path delay is determined as a difference between the measured first and second delays.

REFERENCES:
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patent: 6314537 (2001-11-01), Oh

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