Biquadratic basic cell for programmable analog...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression

Reexamination Certificate

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C327S103000, C327S553000, C327S341000, C327S563000, C330S303000, C330S252000

Reexamination Certificate

active

06239653

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an elementary biquadratic cell for programmable time-continuous analog filters.
2. Discussion of the Related Art
Reference will be made hereinafter in particular, but not exclusively, to signal analog filters for applications related to the reading phase of data from mass memories (also referred to in the technical literature as ‘disk-drive applications’). In this field, the filter cutoff frequencies referred to herein are currently on the order of 50 to 100 MHZ. As is well known, the provision of integrated electronic filters in high-frequency applications cause some problems in using filtering techniques which employ configurations of feedback operational amplifiers intended to provide a desired transfer function. In fact, the frequency limitations of operational amplifiers appear as parasitic single points in the filter transfer function, and this limits the filter performance. These problems can be circumvented at certain frequencies by using open ring configurations, such as filters formed by transconductors and capacitors, referred to as gm/C's for brevity.
Most analog filters can be formed by elementary cells of the low-pass type. For example,
FIG. 1
shows a biquadratic cell
10
according to the prior art. The cell
10
has first, second, third and fourth differential transconductors
1
-
4
, connected in parallel together between a pair of input terminals I
1
, I
2
and a pair of output terminals O
1
, O
2
of the biquadratic cell
10
. Each differential transconductor,
1
,
2
,
3
and
4
, has a respective transconductance value gm
1
, gm
2
, gm
3
and gm
4
, and has first and second input terminals, I+ and I−, and first and second output terminals, O+ and O−, respectively.
The first and second differential transconductors
1
and
2
have their output terminals connected to a voltage reference, specifically a signal ground GND, through a first pair of capacitors, C
1
and C
1
′, and through a second pair of capacitors C
2
and C
2
′, respectively. Also, the third and fourth differential transconductors
3
and
4
have their output terminals feedback connected to the output terminals of the second
2
and the first
1
differential transconductor
4
, respectively. From a functional standpoint, the fourth differential transconductor
4
, and the first capacitor pair C
1
, C
1
′, operate as a pure integrator, whereas the second and third differential transconductors
2
and
3
, and the second capacitance pair C
2
, C
2
′ operate as a damped integrator.
It should be noted that the third differential transconductor
3
, being closed into a unitary feedback, is equivalent to a resistor having a value of 1/gm
3
. In addition, the first differential transconductor
1
provides the needed voltage-to-current conversion at the input of the biquadratic cell
10
.
Each differential transconductor
1
,
2
,
3
and
4
is implemented as a symmetrical differential structure, shown in FIG.
2
.
In particular, the differential transconductor
1
of
FIG. 1
is shown in
FIG. 2
, for example, which is coupled between a supply voltage reference Vdd and the ground GND. The differential transconductor
1
has a pair of input terminals I+ and I− and a pair of output terminals O+ and O−, its structure being symmetrical with respect to an internal node X.
The differential transconductor
1
includes respective bias current generators G
1
and G
2
which are respectively coupled between the supply voltage reference Vdd and respective bipolar transistors T
1
and T
2
, the latter having their base terminals respectively connected to the input terminals I− and I+ and their collector terminals respectively connected to the output terminals O− and O+. The differential transconductor
1
further includes respective resistors R
1
, R
2
of same value R, which are respectively coupled between the emitter terminals of the bipolar transistors T
1
, T
2
and the internal node X, the latter being connected to the ground GND through a common bias current generator GC. In particular, these resistors R
1
, R
2
may advantageously be MOS transistors working in their linear zone.
The differential structure of the transconductor
1
of
FIG. 2
allows the equivalent transconductance value Gmeq of the differential transconductor
1
to be varied by changing the value R of the resistors R
1
and R
2
; the Gmeq value being given by the following equation:
G
meq=gmbip/(1+gmbip*
R
)  (1)
where R is the value of the resistors R
1
and R
2
; and gmbip is the transconductance value of the bipolar transistors T
1
and T
2
.
Thus, by using resistors R
1
, R
2
formed of MOS transistors, the value R can be varied in a simple manner by changing a tuning current for such MOS transistors.
It should be noted that the current draw of a biquadratic cell is the same as that of four differential transconductors, which transconductors must be dimensioned to suit the linear performance required for a given dynamic range of the signals to be processed. In fact, since the behavior of the transconductor stages cannot be linearized by the provision of appropriate feedback loops, the input signal is only required to modulate a small fraction of the current at rest through the active components, including essentially the bipolar transistors.
For example, for an input dynamic range of 400 differential mVp−p and a 1% distortion of the current output from the transconductor stage, the product gmbip*R of Equation 1 should correspond to a value of six, meaning that the differential transconductor has a degeneration of 150 mV relative to the bipolar transistor. When minimal capacitances C
1
, C
2
, i.e. capacitances in the picoFarad range, are used in order to have the parasitic capacitances adequately controlled, currents in the mA range must be used for each differential transconductor to provide comparable time constants with those normally used in such applications.
It must also be noted that the differential transconductor distortion is unrelated to the frequency of the signals being processed. That is, the current within the bipolar transistors incorporated into the differential transconductors is modulated, even for low frequency signals, to produce a variation in their transconductance values and, hence, a distortion in the output current.
The underlying technical problem which is addressed by this invention is the problem of providing a biquadratic cell structure adapted to form continual time filters having such structural and functional features to decrease the power dissipation through the filter, while retaining the performance level, in terms of dynamic speed, of the processed signal and the total harmonic distortion (THD) of the prior art filter.
SUMMARY OF THE INVENTION
The present invention provides a biquadratic cell which has a symmetrical structure and a smaller number of bias branches than conventional ones, and at the same time reduces the current-flowing through each bias branch.
According to one aspect of the invention, an elementary biquadratic cell for programmable time-continuous analog filters is disclosed. The biquadratic cell is coupled between a first voltage reference and a second voltage reference and has at least one pair of input terminals and first and second pairs of output terminals. The cell includes a pair of half-cells, which half-cells are structurally identical with each other. Each half-cell comprises at least a first transistor coupled between the first and the second voltage reference and having a base terminal connected to a respective one of the input terminals. Each half-cell further comprises second and third transistors coupled between the first and second voltage references. The second transistor has a base terminal connected to the first output terminal of the first pair of output terminals and a collector terminal connected to the first output terminal of the second pair of outpu

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