Bipolar transistor with reduced emitter to base capacitance

Details Bipolar transistor with reduced emitter to base capacitance Bipolar transistor with reduced emitter to base capacitance

2002-07-10

2004-08-10

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Bipolar transistor

C257S019000, C257S020000, C257S039000, C257S047000, C257S205000, C257S242000, C257S249000

Reexamination Certificate

active

06774411

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More particularly, the present invention is in the field of fabrication of heterojunction bipolar transistors.
2. Related Art
In a silicon-germanium (“SiGe”) heterojunction bipolar transistor (“HBT”), a thin silicon-germanium layer is grown as the base of a bipolar transistor on a silicon wafer. The silicon-germanium HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Cutoff frequencies in excess of 100 GHz, which are comparable to the more expensive gallium-arsenide based devices, have been achieved for the silicon-germanium HBT.
The higher gain, speed and frequency response of the silicon-germanium HBT are possible due to certain advantages of silicon-germanium, such as a narrower band gap and reduced resistivity. These advantages make silicon-germanium devices more competitive than silicon-only devices in areas of technology where superior speed and frequency response are required.
But as with other transistors, excess capacitance can detrimentally impact performance of the silicon-germanium HBT transistor, primarily by reducing its speed. One form of excess capacitance associated with the silicon-germanium HBT is emitter to base capacitance. The practical effect of a capacitor is that it stores electrical charges that are later discharged, and the extra time required to charge and discharge the excess capacitance slows down the transistor. Because the benefits of high gain and high speed can be compromised by such excess capacitance, it is a goal of silicon-germanium HBT design to reduce such excess capacitance to a minimum. For instance, by keeping the emitter to base capacitance low, improved transistor performance is achieved.
Capacitance develops, for example, when two plates made of an electrically conducting material are separated by a dielectric such as silicon dioxide (“SiO
2
”). In general, capacitance is determined by the geometry of the device and is directly proportional to the area of overlap between the conductive plates and inversely proportional to the distance, or thickness, separating the two plates. Generally, capacitance is calculated using the equation:
Capacitance (
C
)=&egr;
0
kA/t
  (Equation 1)
where &egr;
0
is the permitivity of free space, k is the dielectric constant of the dielectric separating the two plates, A is the area of overlap between the plates, and t is the thickness or separation between the two plates. From the equation, it is seen that reducing the area of overlap between the two plates could lower the capacitance. Alternatively, separating the plates with a dielectric material having a relatively lower dielectric constant k, or increasing the thickness t, of the dielectric material could also lower the capacitance.
FIG. 1
shows an NPN silicon-germanium HBT structure
100
, which is used to describe the emitter to base capacitance, or emitter-base capacitance, found in a silicon-germanium HBT fabricated using conventional fabrication processes. Certain details and features have been left out of
FIG. 1
which are apparent to a person of ordinary skill in the art. Structure
100
includes, among other components, collector
130
, base region
120
, and emitter
140
. In exemplary structure
100
, collector
130
is N type single-crystal silicon which can be deposited epitaxially using a reduced pressure chemical vapor deposition (“RPCVD”) process, and base region
120
is P type single-crystal silicon-germanium deposited epitaxially in a nonselective RPCVD process. As seen in
FIG. 1
, base region
120
is situated on top of, and forms a junction with, collector
130
. Extending out from either side of base region
120
are extrinsic base region
122
and extrinsic base region
124
. In exemplary structure
100
, emitter
140
, which is situated above and forms a junction with base region
120
, is comprised of N type polycrystalline silicon. The interface between emitter
140
, base region
120
, and collector
130
is the active region of the silicon-germanium HBT. Active region width
145
is substantially the same as the distance between dielectric segment
172
and dielectric segment
174
. As is known in the art, proper control of the dimension of active region width
145
is critical for optimal performance of the silicon-germanium HBT.
The portions of emitter
140
extending beyond active region width
145
overlap polycrystalline silicon segment
162
and polycrystalline silicon segment
164
. The portions of emitter
140
extending beyond active region width
145
are referred to as extrinsic emitter region
142
and extrinsic emitter region
144
. Thus, extrinsic emitter region
142
is the region of emitter
140
which is between dashed line
192
and the edge of emitter
140
. Similarly, extrinsic emitter region
144
is the region of emitter
140
which is between dashed line
194
and the edge of emitter
140
. As seen in
FIG. 1
, sandwiched between polycrystalline silicon segment
162
and extrinsic base region
122
, and between polycrystalline silicon segment
164
and extrinsic base region
124
are dielectric segment
172
and dielectric segment
174
. Besides defining active region width
145
, dielectric segments
172
and
174
provide electrical isolation to emitter
140
from base region
120
.
As further seen in
FIG. 1
, buried layer
114
, which is composed of N+ type material, is formed in semiconductor substrate
110
. Collector sinker
112
, also composed of N+ type material, is formed by diffusion of heavily concentrated dopants from the surface of collector sinker
112
down to buried layer
114
. Buried layer
114
and collector sinker
112
provide a low resistance electrical pathway from collector
130
through buried layer
114
and collector sinker
112
to a collector contact (not shown). Deep trench structures
116
and field oxide region
180
, field oxide region
182
, and field oxide region
184
provide electrical isolation from other devices on semiconductor substrate
110
. Although field oxide regions
180
,
182
, and
184
comprise silicon dioxide in the present example, it is known in the art that field oxide regions
180
,
182
, and
184
could be other types of isolation, for example shallow trench isolation regions, deep trench isolation, or local oxidation of silicon, generally referred to as “LOCOS”.
Emitter to base capacitance (“C
eb
”) in a silicon-germanium HBT is composed of intrinsic and extrinsic components. These intrinsic and extrinsic components of the emitter to base capacitance are shown in FIG.
1
. Intrinsic C
eb
150
is between emitter
140
and single-crystal silicon-germanium base region
120
of the silicon-germanium HBT. Intrinsic C
eb
150
is the emitter-base junction capacitance inherent in the silicon-germanium HBT device and is determined by various fabrication parameters in the silicon-germanium HBT device. Therefore, intrinsic C
eb
150
can only be reduced by altering the fabrication parameters and the performance of the device itself. For example, reduction in intrinsic C
eb
150
could be achieved by making active region width
145
narrower, but such a modification to the device architecture would alter the performance properties of the device.
Continuing with
FIG. 1
, extrinsic components of emitter to base capacitance in a silicon-germanium HBT develop where extrinsic emitter region
142
and extrinsic emitter region
144
overlap, respectively, extrinsic base region
122
and extrinsic base region
124
directly through dielectric segment
172
and dielectric segment
174
. More specifically, extrinsic C
eb
152
is between extrinsic emitter region
142
and extrinsic base region
122
through dielectric segment
172
, while extrinsic C
eb
154
is between extrinsic emitter region
144
and extrinsic base region
124
through dielectric segment
174
. The total value of emitter to base capacitance

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