Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-11-04
2004-05-04
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S527000, C257S557000, C257S558000, C257S585000, C257S586000
Reexamination Certificate
active
06730981
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, to a semiconductor device including a bipolar transistor.
2. Description of the Background Art
A method of manufacturing a conventional semiconductor device including a bipolar transistor will now be described. First, as shown in
FIG. 15
, an N
−
epitaxial layer
102
is formed on a semiconductor substrate
101
. A field oxide film
103
is formed on N
−
epitaxial layer
102
.
A polysilicon film (not shown) is formed on semiconductor substrate
101
by CVD (Chemical Vapor Deposition) covering an element formation region of semiconductor substrate
101
separated by field oxide film
103
.
Thereafter, a prescribed impurity to form an external base diffusion layer is implanted into the polysilicon film as shown in FIG.
16
. An external base leading electrode
104
is formed by prescribed etching of the polysilicon film.
As shown in
FIG. 17
, a silicon oxide film
105
is formed on semiconductor substrate
101
by CVD covering external base leading electrode
104
. Then, as shown in
FIG. 18
, a resist pattern
106
is formed on silicon oxide film
105
.
An opening
125
to be a base region is formed by anisotropic etching of silicon oxide film
105
and external base leading electrode
104
using resist pattern
106
as a mask. During this step, a surface portion of N
−
epitaxial layer
102
is etched to some extent.
As shown in
FIG. 19
, by an oxidation, impurity implanted into external base leading electrode
104
is diffused from a surface of N
−
epitaxial layer
102
to the inside, and an external base diffusion layer
108
is formed. In this step, a relatively thin silicon oxide film
107
is formed on a region such as an exposed surface region of N
−
epitaxial layer
102
.
Thereafter, as shown in
FIG. 20
, a prescribed impurity to form an intrinsic base diffusion layer is implanted into N
−
epitaxial layer
102
as an intrinsic base implantation. Then, a silicon oxide film (not shown) is formed on silicon oxide film
105
with the CVD method. By performing anisotropic etching of the silicon oxide film and exposing the surface of N
−
epitaxial layer
102
, a sidewall oxide film
109
is formed as shown in FIG.
21
.
As shown in
FIG. 22
, a polysilicon film
110
(or an amorphous silicon film) is formed on silicon oxide film
105
with the CVD method. Then, a prescribed impurity to form an emitter diffusion layer is implanted into polysilicon film
110
as an emitter implantation.
As shown in
FIG. 23
, an emitter leading electrode
110
a
is formed by a prescribed patterning of polysilicon film
110
. An interlayer silicon oxide film
111
is formed with the CVD method so as to cover emitter leading electrode
110
a.
Thereafter, the impurity implanted as the intrinsic base implantation is diffused by a heat treatment to form an intrinsic base diffusion layer
112
. The impurity implanted as the emitter implantation is diffused to form an emitter diffusion layer
113
.
As shown in
FIG. 24
, prescribed contact holes
111
a
-
111
c
are respectively formed by prescribed etching of interlayer silicon oxide film
111
. Then, an aluminum film (not shown) is formed with sputtering, for example, to fill contact holes
111
a
-
111
c.
As shown in
FIG. 25
, a collector electrode
116
, a base electrode
114
and an emitter electrode
115
are respectively formed by a prescribed patterning of the aluminum film. As a result, a semiconductor device including a bipolar transistor T is formed.
The conventional semiconductor device has, however, problems as follows. Intrinsic base diffusion layer
112
is formed in the step shown in
FIG. 23
by a heat treatment of the prescribed impurity which was implanted into N
−
epitaxial layer
102
in the step shown in FIG.
20
.
To ensure an electrical connection between intrinsic base diffusion layer
112
formed as such and external base diffusion layer
108
, it is necessary to diffuse the impurity for external base diffusion layer
108
to a deeper region of semiconductor substrate
101
, and to make the etched amount (removed amount) of the surface portion of N
−
epitaxial layer
102
as small as possible when opening
125
for the base region is formed.
In the step shown in
FIG. 19
, on the other hand, when the impurity for external base diffusion layer
108
is to be diffused to a deeper region of N
−
epitaxial layer
102
by a heat treatment while making small the removed amount of the surface portion of N
−
epitaxial layer
102
located on the bottom of opening
125
, the impurity will also be diffused to a lateral (horizontal) direction.
That is, the impurity will be diffused toward a portion of N
−
epitaxial layer
102
located near a center of the bottom of opening
125
, as well as toward a portion of N
−
epitaxial layer
102
located directly below field oxide film
103
.
Particularly, when the impurity is diffused toward the portion of N
−
epitaxial layer
102
located near the center of the bottom of opening
125
, a distance L between external base diffusion layer
108
and emitter diffusion layer
113
becomes smaller as shown, for example, in FIG.
23
. As a result, breakdown voltage between the emitter and base decreases.
In addition, an injection efficiency of the emitter decreases in a portion around emitter diffusion layer
113
, and a current gain hFE decreases when the distance L becomes smaller.
Furthermore, an impurity concentration in intrinsic base diffusion layer
112
around emitter diffusion layer
113
is affected by the distance L between external base diffusion layer
108
and emitter diffusion layer
113
depending on the size of the bipolar transistor. Consequently, an injection efficiency of electrons and the current gain hFE vary around emitter diffusion layer
113
.
SUMMARY OF THE INVENTION
The present invention is made to solve the above-described problems. An object of the present invention is to provide a semiconductor device which suppresses decrease in breakdown voltage between an emitter and a base and suppresses decrease and variation of current gain hFE.
A semiconductor device according to the present invention includes an element formation region formed on a main surface of a semiconductor substrate of a first conductivity type, an insulator film, an opening, a first conductive material portion, a first impurity region of a first conductivity type, a second conductive material portion, a second impurity region of a second conductivity type, and a third impurity region of a second conductivity type. The element formation region formed on the main surface of the semiconductor substrate is separated by an element isolation insulator film. The insulator film is formed on the semiconductor substrate so as to cover the element formation region. The opening is formed in the insulator film and the element formation region, and has a sidewall and a bottom exposing a region of the semiconductor substrate located approximately on the center portion of the element formation region. The first conductive material portion is formed between the semiconductor substrate and the insulator film, and extends from a side of the element isolation insulator film to the opening and is exposed at the sidewall of the opening. The first impurity region of the first conductivity type is formed on a surface portion of the semiconductor substrate exposed at the bottom of the opening. The second conductive material portion is electrically connected to the first impurity region. The second impurity region of the second conductivity type is formed on the semiconductor substrate so as to enclose the first impurity region from side and bottom, and to include the surface portion of the semiconductor substrate exposed at the bottom of the opening. The third impurity region of the second conductivity type is formed on a surface portion of the semiconductor substrate within the element formation regio
Leydig , Voit & Mayer, Ltd.
Renesas Technology Corp.
Tran Minhloan
Tran Tan
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