Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – Plural non-isolated transistor structures in same structure
Reexamination Certificate
1998-07-09
2001-04-24
Pham, Long (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
Plural non-isolated transistor structures in same structure
C257S592000
Reexamination Certificate
active
06222250
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device comprised of vertical NPN transistors and vertical PNP transistors formed on one and the same substrate for forming a complementary bipolar transistor, and a method for manufacturing the same. More particularly, it relates to a method for forming a high performance complementary bipolar transistor simply by supplementing a minimum number of steps to the conventional method for manufacturing bipolar transistors.
2. Description of the Related Art
A complementary bipolar transistor, which is a combination of a NPN transistor and a PNP transistor, has been employed up to now in a high-output amplifier stage of an audio equipment as a component of e.g., a push-pull circuit. In a amplifier/detector circuit for intermediate frequency for pictures for UHF television tuner or an LSI for high frequency represented by a signal processing circuit for high-speed communication or optical communication, the tendency is towards realization of a system-on-chip. In keeping up therewith, a there is a demand for a method for manufacturing a complementary bipolar transistor circuit of higher speed and higher integration degree with a smaller number of steps.
FIG. 1
shows a typical construction of a conventional representative complementary bipolar transistor. With the present bipolar transistor, there are formed a vertical NPN transistor (V-NPNTr) and a vertical PNP transistor (V-PNPTr) on one and the same substrate. With V-NPNTr and V-PNPTr, the emitter/base/collector junction is formed along the depth of the substrate, that is in the vertical direction.
In a V-NPNTr portion towards left in
FIG. 1
, a n
+
type buried collector region
3
(n
+
-BL)is formed in a boundary region between a p-type substrate (p-Sub)
1
and a n-type epitaxial layer
5
(n-EPI) formed thereon. The n-type epitaxial layer
5
has its upper layer portion divided into plural island-like device-forming regions by device separating regions
7
formed by the LOCOS method (selective oxidization separation). A p-type base region
10
and a n
+
type collector contact region
9
connecting to the buried collector region
3
are formed on an upper surface portion of the device forming region.
The upper surfaces of the device-forming regions are contacted by three different sorts of contact electrodes formed by polysilicon layers via an interlayer insulating layer
13
. That is, the portion of the upper surface facing the base region
10
is contacted by an emitter contact electrode
14
E
n
and a base contact electrode
14
B
n
, where the suffix n refers to an NPN transistor. By impurity diffusion from these electrodes, n
+
type emitter region
15
E
n
and a p
+
type base contact region
15
B
n
are formed within the base region
10
. The portion of the upper surface facing the collector region
9
is contacted by a collector contact electrode
14
C
n
, and a n type collector contact region
15
C
n
is formed by impurity diffusion from this electrode
14
C
n.
To these contact electrodes
14
E
n
,
14
B
n
and
14
C
n
, there are connected, via openings formed in the SiO
2
interlayer insulating film
16
, an emitter electrode
17
E
n
, a base electrode
17
B
n
and a collector electrode
17
C
n
, each of which is formed by an Al-based multi-layer film.
In a V-PNPTr portion towards right in
FIG. 1
, an n type buried separating region
2
(N-pocket) for electrically separating the transistor from the substrate and a p
+
type buried collector region
4
C are formed in this order in a boundary region between the p-type substrate (p-Sub)
1
and the n-type epitaxial layer
5
(n-EPI) formed thereon. On the buried collector region
4
C is formed a p-type well
6
by ion implantation into the n-type epitaxial layer. This p-type well
6
has its upper surface layer divided into plural island-like device forming regions by the device separating regions
7
formed by LOCOS (selective oxidative separation). On the surface layer portion of the device forming region, there are formed an n-type base region
11
and a p
+
type collector contact region
8
C connecting to the p
+
type buried collector region
4
C.
The upper surface of the device forming region is contacted by three sorts of polysilicon layer contact electrodes via the SiO
2
interlayer insulating layer
13
. That is, the upper surface portion facing the base region
11
is contacted by an emitter contact electrode
14
E
p
and a base contact electrode
14
B
p
, where the subscript p refers to the PNP transistor. By impurity diffusion or ion implantation from these electrodes, the p
+
type emitter region
15
E
p
and the n
+
type base contact region
15
B
p
are formed in the base region
11
. The upper surface portion facing the collector contact region
8
C is contacted by the collector contact electrode
14
C
p
, and a p
+
type collector contact electrode
15
C
p
is formed by impurity diffusion from this electrode
14
C
p.
To these contact electrodes
14
E
p
,
14
B
p
and
14
C
p
are connected the emitter electrode
17
E
p
, base electrode
17
B
p
and the collector electrode
17
C
p
, each formed by Al-based multi-layer films, via openings formed in the SiO
2
interlayer insulating film
16
, respectively.
The V-NPNTr and the V-PNPTr are separated from each other, as are other devices, not shown, by a p
+
type channel stop layer formed on the lower side of the device separating region
7
. The channel stop layer is made up of a lower layer side channel stop layer
4
ISO and an upper layer side channel stop layer
8
ISO stacked back-to-back as an upper tier and a lower tier.
The production process for the above-described complementary bipolar transistor is prolonged and complicated as compared to the production process for the usual bipolar transistor because of the necessity of forming the n-type buried separation layer
2
for electrically separating the p
+
buried collector region
4
C of the V-PNPTr from the p-type substrate. Since this buried separating region
2
needs to be of the maximum thickness possible and formed at as deep a site in the substrate as possible, it is usually formed in the p-type substrate
1
at the outset by gasphase diffusion of n-type impurities. However, during the drivein of the n
+
type buried contact region
3
, which represents the severest prolonged high-temperature heat-treatment process of the production process for the complementary bipolar transistor, the buried separating region
2
is diffused upwardly into the inside of the n-type epitaxial layer
5
. Consequently, the n-type epitaxial layer
5
needs to be of a certain thickness.
On the other hand, the p
+
buried collector region
4
C of the V-PNPTr is also responsible for the increased thickness of the n-type epitaxial layer
5
. The p
+
type buried collector region
4
C is usually formed in advance of the n-type epitaxial layer
5
. During the epitaxial growth carried out at a temperature of 1000° to 1100° C., the p
+
type buried collector region
4
C is diffused upwardly by heat diffusion and auto-doping. In addition, the LOCOS step of forming the device separating region in the n-type epitaxial layer is the second severest prolonged high-temperature heat-treatment process of the production process of the complementary bipolar transistor. That is, the n-type epitaxial layer
5
needs to be increased in thickness in order to take into account the fact that the buried collector region
4
C undergoes upward diffusion in the course of the LOCOS process.
Thus the n-type epitaxial layer needs to be increased in thickness for improving characteristics of the V-PNPTr. However, this leads to increased size of the collector layer of the V-NPNTr and hence to base-widening effects of Kirk-effects, resulting in lowered cut-off frequency and lowered operating speed.
In addition, with the above-described production process, two ion implantation steps are employed for forming the channel
Coleman William David
Kananen Ronald P.
Pham Long
Rader Fishman & Grauer
Sony Corporation
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