Patent
1991-03-05
1992-06-09
Wojciechowicz, Edward J.
357 54, 357 55, 357 59, 357 67, 357 68, H01L 2972
Patent
active
051211840
ABSTRACT:
In a process for fabricating a bipolar transistor with a single polysilicon layer, a silicon nitride layer 22 and a phospho-silicate glass layer 24 are formed on top of the polysilicon layer and the link oxide layers. The glass layer 24 has a high etch selectivity compared to the nitride layer 22 so that the glass layer may be overetched above the emitter polysilicon region without overetching the link oxide. The nitride layer is then removed by etching without significantly affecting the link oxide layer. Thus the emitter metal contact may be self-aligned on top of the emitter polysilicon region 14, 114.
REFERENCES:
patent: 4516147 (1985-05-01), Komatsu et al.
patent: 4782030 (1988-11-01), Katsumata et al.
patent: 4979010 (1990-12-01), Brighton
Brigham Kristin
Huang Wen-Ling M.
Hewlett--Packard Company
Wojciechowicz Edward J.
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