Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With specified electrode means
Reexamination Certificate
2000-10-17
2004-08-17
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With specified electrode means
C257S362000
Reexamination Certificate
active
06777784
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device structures and, in particular, to electrostatic discharge protection structures for use with integrated circuits.
2. Description of the Related Art
Electrostatic Discharge (ESD) protection devices are commonly employed in an integrated circuit (IC) to protect electronic devices in the IC from spurious pulses of excessive voltage (e.g., an ESD event, Human Body Model [HBM] event, or Electrical Overstress [EOS] event). See, for example, S. M. Sze,
Electrostatic Discharge Damage
, in VLSI Technology, Second Edition, 648-650 (McGraw Hill, 1988). A variety of conventional ESD protection devices that make extensive use of diodes, metal-oxide-semiconductor field effect transistors (MOSFETS) and bipolar transistors are known in the field.
Conventional bipolar transistor-based ESD protection devices include, for example, bipolar transistor-based transient and bipolar transistor-based static ESD protection devices (e.g., grounded base bipolar transistor-based ESD protection devices and Zener Triggered bipolar transistor-based ESD protection devices). Descriptions of these and other conventional ESD protection structures are available in G. Croft and J. Bernier,
ESD Protection Techniques for High Frequency Integrated Circuits
, Microelectronics Reliability 38, 1681-1689 (1998);
Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS/Bipolar Circuits
, J. Z. Chen et al.,
Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS/Bipolar Circuits,
34
th
Annual IEEE International Reliability Physics Symposium Proceedings, 227-232 (1996); J. C. Bemier et al.,
A Process Independent ESD Design Methodology
, IEEE International Symposium on Circuits and Systems Proceedings 1, 218-221 (1999); W. D. Mack et al.,
New ESD Protection Schemes for BiCMOS Processes with Application to Cellular Radio Designs
, IEEE International Symposium on Circuits and Systems 6, 2699-2702 (1992), each of which is hereby fully incorporated by reference.
FIG. 1
is a cross-sectional view of a conventional bipolar transistor-based ESD protection structure
10
. Conventional bipolar transistor-based ESD protection structure
10
includes a P-type substrate
12
, an N-type collector region
14
, a P-type base region
16
(e.g., a P-type Si—Ge base region) and an N-type polysilicon emitter
18
. The conventional bipolar transistor-based ESD protection structure
10
also includes electrical isolation regions
20
and
22
. A metal base contact
24
makes contact with the P-type base region
16
via polysilicon line
26
. A metal emitter contact
28
is in contact with the N-type polysilicon emitter
18
, while a metal collector contact
30
is in contact with the N-type collector region
14
. The metal base contact
24
, the metal emitter contact
28
and the metal collector contact
30
each extends through dielectric layer
32
.
Electrical schematics illustrating this conventional bipolar transistor-based ESD protection structure
10
arranged in a grounded base bipolar transistor-based ESD protection device and a Zener Triggered bipolar transistor-based ESD protection device are provided in
FIGS. 2A and 2B
, respectively.
A significant physical limitation of conventional bipolar transistor-based ESD protection structures is their susceptibility to thermal overheating and associated irreversible damage (e.g., local melting). As a consequence, conventional bipolar transistor-based ESD protection structures are unstable in the event that a critical temperature of approximately 1300° K is reached during an ESD event. Still needed in the field, therefore, is an ESD protection structure for use with bipolar or BiCMOS ICs that is relatively immune to thermal overheating and, thus, stable during an ESD event.
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G.Meneghesso, J.R.M. Luchies, F.G. Kuper and A.J. Mouthaan, Turn-On Speed of Grounded Gate NMOS ESD Protection Transistors 1996, pp. 1735-1738.*
Minh Tong, Robert Gauthier and Vaughn Gross, Study of Gated PNP As an ESD Protection Device for Mixed-Voltage and Hot-Pluggable Circuit Applications, IBM Microelectronics Division, pp 6.3.1-6.3.5.*
G. Croft et al.,ESD Protection Techniques for High Frequency Integrated Circuits, Microelectronics Reliability 38, 1998, pp. 1681-1689.
J. Z. Chen et al.,Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS-Bipolar Circuits, 34th Annual IEEE International Reliability Physics Symposium Proceedings, 1996, pp. 227-232.
J.C. Bernieret al.,A Process Independent ESD Design Methodology, IEEE International Symposium on Circuits and Systems Proceedings 1, 1999, pp. 218-221.
W.D. Mack et al.,New ESD Protection Schemes for BiCMOS Processes with Application to Cellular Radio Designs, IEEE International Symposium on Circuits and Systems 6, 1992, pp. 2699-2702.
Hopper Peter J.
Vashchenko Vladislav
Farahani Dana
National Semiconductor Corporation
Pickering Mark C.
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