Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure
Reexamination Certificate
2002-10-10
2003-12-16
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
C257S197000, C257S198000, C257S586000
Reexamination Certificate
active
06664610
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Filed of the Invention
This invention relates to a bipolar transistor, especially relates to a hetero-junction bipolar transistor (HBT) made of a combination of III-V compound semiconductor materials.
2. Related Prior Art
HBT is applying to an amplifier device for a high-speed optical communication system. Although HBT has intrinsically an excellent characteristic in high-frequency band over 10 GHz, further performance is requested in frequency band over 40 GHz. One solution to realize such superior performance is to reduce an area of a sub-collector layer or a collector layer to decrease the capacitance between the collector and the base electrode.
A subject accompanying with the conventional HBT and its manufacturing process is explained as referring FIG.
11
.
An InGaAs sub-collector is grown on an InP substrate and formed to a sub-collector mesa by an etching (FIG.
11
(D)). Subsequently layer of an InGaAs collector, an InGaAs base, an InP emitter, and an InGaAs emitter contact are formed so as to cover the sub-collector mesa with an octagonal shape as shown in FIG.
11
(B). Cross sections of these layers are bent upwardly and downwardly at both edges of the sub-collector mesa by reflecting the shapes thereof. Further, various crystal surfaces, such as {
111
}, {
211
} and {
331
}, appear in edge surfaces of the octagonal mesa.
Forming the emitter contact mesa by etching, a large number of etching-pit comes out, especially in boundaries between {
211
} and {
100
}, and also between {
331
} and {
100
}. This is due to a reason that the etching is promoted at these boundaries. Further, since the thickness of the emitter is only several tenth of nano-meter, etching-pits pierce the emitter and reach the base beneath the emitter. This fails the reliability and the yield of the HBT.
SUMMARY OF THE INVENTION
An object of the claimed invention is to provide a new configuration of the HBT and a method of producing the HBT. To solve the subject, the present HBT comprises a sub-collector layer on a predetermined surface orientation of a semiconductor substrate, a collector layer on the sub-collector layer, a base layer on the collector layer, an emitter layer on the base layer and an emitter contact layer on the emitter layer. The sub-collector layer has a pair of edges along predetermined axis of the substrate and subsequent layer of the collector, the base, and the emitter layer covers these edges of the sub-collector so as to make planar the surface of the emitter layer. Since the surface of the emitter layer is planar, the generation of etching-pits on the emitter layer can be prevented. Moreover, it is preferable that the emitter contact layer comprises two portions, one portion has a first carrier concentration and contact to the emitter layer, the other portion has a second carrier concentration greater than the first concentration and contacts to the emitter electrode. This directs the lower contact resistance, thus enhances the high frequency performance of the HBT.
Next aspect of the present HBT comprises a collector layer on a semi-insulating semiconductor substrate with a predetermined surface orientation, a base layer on the collector layer, an emitter layer on the base layer, and an emitter contact layer on the emitter layer. The collector layer forms a mesa shape with a cross section of a trapezium, and subsequently layers are formed so as to cover the collector mesa. Further, since the surface of the emitter layer is planar, the appearance of etching-pits on the emitter layer can be prevented even when edges of the emitter layer is apart from edges of the emitter contact layer. In this configuration, the thickness of the base layer at the position just above the collector layer is thinner than the thickness at the position peripheral to the collector layer. This directs the reduction of the base resistance, thus enhances the high frequency performance of the HBT.
Another aspect of the present invention relates to the method for producing the HBT having the described configuration. The method comprises steps of: 1) etching the sub-collector film deposited on the semiconductor substrate and forming a pair of depression in the sub-collector film, intrinsic region for the operation of HBT is formed therebetween. 2) Forming the collector film so as to plug depressions. 3) Forming the base film, the emitter film, and the emitter contact film on the contact film. 4) Etching the emitter contact film so as to expose portions of the emitter film both sides of the emitter contact layer. Because of the planar surface of the emitter film, etching-pits generated in the etching of the emitter contact film can be reduced. Depressions formed in the sub-collector are along a predetermined crystal axis on the substrate, and the width of the depression is prefer to be greater than 0.5 um and smaller than 2.0 um at the bottom of it. Further, it is preferable to form the contact film, the base film, the emitter film and the emitter contact film by the Metal Organized Chemical Vapor Deposition (MOCVD) technique. To use the MOCVD technique enables to plug depressions in the sub-collector film and to make a planar surface of the emitter film.
Still another aspect of the preset invention also relates to the method of the manufacturing process of the HBT. Another method comprises steps of, 1) etching the collector film deposited on the semiconductor substrate and forming a pair of depressions therein, the intrinsic region of the HBT is formed therebetween. 2) Forming the base film so as to plug depressions. 3) Forming subsequently films of the emitter film and the emitter contact film on the base film. Lastly, 4) etching the emitter contact film to make the emitter contact layer and to expose the surface of the emitter film on both sides of the emitter contact layer. The planar surface of the base layer prevents from bringing etching-pits on the emitter film. This enhances the reliability and the yield of the HBT.
The etching of the sub-collector film or the collector film is preferable to be done by a wet etching using a specific solution, which forms side edges of depressions to be normal mesa shapes and opening of the depression is wider than the bottom thereof. Therefore, plugging of depressions is facilitated, thus the planar surface of subsequently grown film can be obtained.
REFERENCES:
patent: 5834800 (1998-11-01), Jalali-Farahani et al.
patent: 5981985 (1999-11-01), Yang et al.
patent: 2002/0117665 (2002-08-01), Yaegassi et al.
patent: 06-291134 (1994-10-01), None
Miyamoto, et al., “Evaluation of base-collector capacitance in submicron buried metal heterojunction bipolar transistors”, extended abstracts of the 2002 International Conference on Solid State Devices and Materials, Nagoya, 2002, pp. 276-277.
Kawasaki Takeshi
Kotani Kenji
Yaegashi Seiji
Yanagisawa Masaki
Yano Hiroshi
Prenty Mark V.
Smith , Gambrell & Russell, LLP
Sumitomo Electric Industries Ltd.
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