Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
2001-03-22
2003-11-04
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S257000, C257S198000, C257S200000, C257S580000
Reexamination Certificate
active
06642553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention.
The invention relates to a bipolar transistor as well as to a method of its fabrication.
An important field of application of bipolar transistors are high speed applications. In order to improve the efficiency of transistors in the range of highest speeds, the influence of parasitic components, i.e. resistances and capacitances, must be reduced. For this reason, not only are conductive connections, if possible, required between the metal contacts and the active (internal) region of the transistor but also a minimized passive transistor surface.
2. The Prior Art.
To satisfy these requirements, laterally scaled, so-called “double-process poly-silicon technologies” are used in modern methods of fabrication of vertical bipolar transistors. It is possible in such technologies to arrange the base contact and parts of the highly conductive poly-silicon connection between contact and internal base above insulated regions. A special arrangement of this kind in which the base has been fabricated epitaxially over an etched semiconductor region is described in U.S. Pat. No. 5,137,840. Relative to “single-process poly-silicon technologies” these structural advantages unfortunately entail such drawbacks as additional processing complexity and heightened contact resistances. These drawbacks are rooted in the required etching of the poly-silicon in the active transistor region as well as in the out-diffusion of the dopants from the highly doped poly-silicon layer into the monocrystalline base connection region. Since the poly-silicon for the base connection region over the active transistor region is removed by dry etching techniques and since there is no selectivity as to the monocrystalline silicon therebelow, the exposed silicon surface is likely to be damaged. Surface roughness, malfunctions of the lattice structure and penetration of foreign substances are the result.
There have been a variety of proposals to overcome these problems. For instance, etch stop layers are used to protect the emitter region in order to solve problems during dry etching. Additional efforts are needed to ensure a self-adjustment of emitter region and etch stop layer.
Lately, it has been possible further to improve the high speed characteristics by the use of epitaxial processes. To this end use is made of in situ doping during precipitation to achieve small base widths, i.e. small thicknesses of the base layers and low base layer resistances.
A further degree of freedom during setting of the base resistance and current amplification and, hence, optimization of the high speed characteristics is obtained by the precipitation of hetero layers.
The concept of double-poly-silicon technology including etch stop layer has also been realized in the case of epitaxially incorporated base layers by so-called selective epitaxy. In epitaxy that epitaxial growth on exposed semiconductor surfaces only is ensured by the conditions of precipitation. If differential epitaxy is used during which silicon material is precipitated on semiconductor as well as insulating regions, it is possible simultaneously to produce the internal base and the connection to a base contact positioned in an insulating region (base connection region). In general, this avoids the need for an additional poly-silicon layer. The resultant quasi double-poly-silicon arrangement makes it possible to simplify the process.
However, compared to a complete double-poly-silicon process one is confronted by the disadvantage of it not being possible to set the thickness of the epitaxial layer in the active transistor region independently of the thickness of the silicon layer. For two different requirements exist as regards the thickness of the epitaxial layer. That is to say that within the active emitter region the layer thickness between the highly doped emitter and the base should be sufficiently thin. In the outer base region a greater thickness is advantageous to provide a low resistance base connection. In order simultaneously to satisfy these opposing requirements, recourse may be had to increasing the thickness of the epitaxial layer above the base (cover thickness) in connection with a selective implantation in the active emitter region. Without appropriate measures the annealing of implantation damage, for instance in the case of epitaxially produced doping of the base in a silicon-germanium layer, leads to an unacceptable widening of the base profile, however. If the cover layer is doped in situ, undesired consequences result in respect of the conventionally used poly-emitter structures: An emitter zone of reduced conductivity or even reduced charge carriers is the usual result below the passivation between the margin of the emitter and the highly doped base connection. This may lead to a deterioration of the static as well as dynamic characteristics of the transistor. A thicker buffer layer between substrate and base may provide partial relief if in situ doping of the collector doping kind is incorporated during epitaxy.
Aside from process related technological difficulties, this variant suffers from the disadvantage, among others, of subsequent redoping of the buffer layer outside the active transistor increasing the base-collector capacitance.
OBJECTS OF THE INVENTION
It is an object of the invention, to propose a bipolar transistor and a method of its fabrication by which, in a single-process, poly-silicon technology using differential epitaxy to produce the base, the described disadvantages of conventional arrangements are overcome, thereby further improving the high speed characteristics in particular, providing connections as conductive as possible between the metal contacts and the active (internal) transistor region as well as a minimized passive transistor surface, while at the same time avoiding additional process complexity and increased contact resistances.
BRIEF SUMMARY OF THE INVENTION
In accordance with the invention the object is accomplished by precipitating a cover layer (
17
,
119
) or a combination of layers (
117
,
118
,
119
) over the base layer (
16
,
116
) and complete or partial removal thereof by means of a partial mask in the active emitter region, whereby a surface relief is wet-chemically formed in the active emitter region.
A single-process poly-silicon bipolar transistor with an epitaxially produced base in accordance with the invention makes reduced external base resistances possible without deterioration of the emitter characteristics. As a result of the uninterrupted precipitation of internal and external base region no interfacial problems occur at the base connection. Moreover, the base-collector capacitance can also be reduced.
An additional in situ doping or hetero layer sequence in the cover over the precipitated base layer offers further advantages. As etch stop layers such intermediate layers affect a balancing of thickness variations of the cover in the active emitter region.
An appropriate doping of the cover layer of the conductive kind of the base which in the active emitter is removed during re-etching of the cover leads to a reduced external base resistance. The self-adjusting arrangement makes possible a low-ohmic base connection free of implantation damage up to very small emitter widths. Moreover, such additional doping of the base connection makes possible smaller distances between the active emitter region and to siliconize the base connection.
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patent: 5137840 (1992-08-01), Desilets et al.
patent: 5552617 (1996-09-01), Hill et al.
patent: 5604374 (1997-02-01), Inou et al.
patent: 5668396 (1997-09-01), Sato
patent: 5798561 (1998-08-01), Sato
patent: 5930635 (1999-07-01), Bashir et al.
patent: 6020246 (2000-02-01), Koscielniak et al.
patent: 6100124 (2000-08-01), Iwamoto
patent: WO 90/09678 (1990-08-01), None
Drews Juergen
Heinemann Bernd
Knoll Dieter
Tillack Bernd
Ho Hoai
Hormann Karl
Institut fuer Halbleiterphysik Frankfurt (Oder) GmbH.
Nguyen Dao H.
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