Bipolar transistor

Details Bipolar transistor Bipolar transistor

2006-11-14

2006-11-14

Richards, N. Drew (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

With base region having specified doping concentration...

C257S586000, C257S588000

Reexamination Certificate

active

07135757

ABSTRACT:
A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

REFERENCES:
patent: 5296391 (1994-03-01), Sato et al.
patent: 5326718 (1994-07-01), Klose et al.
patent: 5391503 (1995-02-01), Miwa et al.
patent: 5422203 (1995-06-01), Guyomard et al.
patent: 5432104 (1995-07-01), Sato
patent: 5504018 (1996-04-01), Sato
patent: 5508537 (1996-04-01), Imai
patent: 5523245 (1996-06-01), Imai
patent: 5599723 (1997-02-01), Sato
patent: 5723378 (1998-03-01), Sato
patent: 5840613 (1998-11-01), Sato
patent: 5897359 (1999-04-01), Cho et al.
patent: 5962880 (1999-10-01), Oda et al.
patent: 6368946 (2002-04-01), Dekker et al.
patent: 6469367 (2002-10-01), Kondo et al.
patent: 0 476 412 (1992-03-01), None
patent: 0 535 350 (1993-04-01), None
patent: 0 600 276 (1994-06-01), None
patent: 0 768 716 (1997-04-01), None
patent: 02295127 (1990-12-01), None
patent: WO 97/37377 (1997-10-01), None
Nauta, B. et al.: “A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter”, IEEE, vol. 30, No. 12, Dec. 1995, pp. 1302-1308.
Bult, K. et al.: “A 170mW 10b 50MSample/s CMOS ADC in 1mm”, IEEE, 1997, pp. 86, 98-99, 378.
Kattmann, K. et al.: “A Technique for Reducing Differential Non-Linearity Errors in Flash A/D Converters”, IEEE, 1991, p. 170.
Vorenkamp, P. et al.: “A 12-b, 60-MSample/s Cascaded Folding and Interpolating ADC”, IEEE, 1997, pp. 1876-1886.
Sato, F. et al.: “Sub-20psec ECL Circuits with 50GHz fmax Self-aligned SiGe HBTs”, IEEE, 1992, pp. 15.2.1-15.2.4.
Ohue, E. et al.: “A 7.7-ps CML Using Selective-Epitaxial SiGe HBTs”, IEEE, 1998, pp. 97-100.
Van de Grift, R. E. J. et al.: “An 8-bit Video ADC Incorporating Folding and Interpolation Techniques”, IEEE, vol. SC-22, No. 6, Dec. 1987, pp. 944-953.
Sato, F. et al.: “A Super Self-Aligned Selectively Grown SiGe Base (SSSB) Bipolar Transistor Fabricated by Cold-Wall Type UHV/CVD Technology”, IEEE, vol. 41, No. 8, Aug. 1994, pp. 1373-1378.
Sato, F. et al.: “Self-Aligned” Selective MBE Technology for High-Performance Bipolar Transistors, IEEE, 1990, pp. 25.7.1-25.7.4.

Affiliated with

Also associated with

Rating

Bipolar transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bipolar transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bipolar transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3661968