Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Patent
1993-09-20
1996-06-11
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
257198, 257565, 257566, 257571, 257618, 437132, H01L 310328, H01L 27082, H01L 2906, H01L 2120
Patent
active
055258174
ABSTRACT:
Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.
REFERENCES:
patent: 3575731 (1971-04-01), Hoshi et al.
patent: 3624454 (1971-11-01), Adkinson et al.
patent: 4731340 (1988-03-01), Chang et al.
patent: 4954457 (1990-09-01), Jambotkar
patent: 5001534 (1991-03-01), Lunardi et al.
patent: 5208184 (1993-05-01), Bayvaktaroglv
Umesh K. Mishra, et al., "Self-Aligned AlInAs-GaInAs Heterojunction Bipolar Transistors and Circuits," IEEE Electron Device Letters, vol. 10, No. 10, Oct. 1989, pp. 467-469.
Hill Darrell G.
Liu William U.
Crane Sara W.
Donaldson Richard L.
Kesterson James C.
Martin Wallace Valencia
Skrehot Michael K.
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